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  mobile low-power ddr sdram mt46h32m16lf C 8 meg x 16 x 4 banks mt46h16m32lf C 4 meg x 32 x 4 banks MT46H16M32LG C 4 meg x 32 x 4 banks features ? v dd /v ddq = 1.70C1.95v ? bidirectional data strobe per byte of data (dqs) ? internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? 4 internal banks for concurrent operation ? data masks (dm) for masking write data; one mask per byte ? programmable burst lengths (bl): 2, 4, 8, or 16 ? concurrent auto precharge option is supported ? auto refresh and self refresh modes ? 1.8v lvcmos-compatible inputs ? temperature-compensated self refresh (tcsr) ? partial-array self refresh (pasr) ? deep power-down (dpd) ? status read register (srr) ? selectable output drive strength (ds) ? clock stop capability ? 64ms refresh, 32ms for automotive temperature table 1: key timing parameters (cl = 3) speed grade clock rate access time -5 200 mhz 5.0ns -54 185 mhz 5.0ns -6 166 mhz 5.0ns -75 133 mhz 6.0ns options marking ? v dd /v ddq C 1.8v/1.8v h ? configuration C 32 meg x 16 (8 meg x 16 x 4 banks) 32m16 C 16 meg x 32 (4 meg x 32 x 4 banks) 16m32 ? addressing C jedec-standard addressing lf C reduced page size 1 lg ? plastic "green" package C 60-ball vfbga (8mm x 9mm) 2 bf C 90-ball vfbga (8mm x 13mm) 3 b5 ? timing C cycle time C 5ns @ cl = 3 (200 mhz) -5 C 5.4ns @ cl = 3 (185 mhz) -54 C 6ns @ cl = 3 (166 mhz) -6 C 7.5ns @ cl = 3 (133 mhz) -75 ? power C standard i dd2 /i dd6 none ? operating temperature range C commercial (0? to +70?c) none C industrial (C40?c to +85?c) it C automotive (C40?c to +105?c) at ? design revision :c notes: 1. contact factory for availability. 2. only available for x16 configuration. 3. only available for x32 configuration. 512mb: x16, x32 mobile lpddr sdram features pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: configuration addressing architecture 32 meg x 16 16 meg x 32 reduced page size 16 meg x 32 configuration 8 meg x 16 x 4 banks 4 meg x 32 x 4 banks 4 meg x 32 x 4 banks refresh count 8k 8k 8k row addressing 8k a[12:0] 8k a[12:0] 16k a[13:0] column addressing 1k a[9:0] 512 a[8:0] 256 a[7:0] figure 1: 512mb mobile lpddr part numbering mt 46 h 32m16 lf bf -6 it :c micron technology product family 46 = mobile lpddr operating voltage h = 1.8/1.8v configuration 32 meg x 16 16 meg x 32 addressing lf = jedec-standard lg = reduced page size package codes bf = 60-ball (8mm x 9mm) vfbga, green b5 = 90-ball (8mm x 13mm) vfbga, green design revision :c = third generation operating temperature blank = commercial (0c to +70c) it = industrial (C40c to +85c) at = automotive (C40c to +105c) power blank = standard i dd2 /i dd6 cycle time (cl = 3) -5 = 5ns t ck -54 = 5.4ns t ck -6 = 6ns t ck -75 = 7.5ns t ck fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. microns fbga part marking decoder is available at www.micron.com/decoder . 512mb: x16, x32 mobile lpddr sdram features pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
contents general description ......................................................................................................................................... 8 functional block diagrams ............................................................................................................................... 9 ball assignments ............................................................................................................................................ 11 ball descriptions ............................................................................................................................................ 13 package dimensions ....................................................................................................................................... 15 electrical specifications .................................................................................................................................. 17 electrical specifications C i dd parameters ........................................................................................................ 20 electrical specifications C ac operating conditions ......................................................................................... 26 output drive characteristics ........................................................................................................................... 31 functional description ................................................................................................................................... 34 commands .................................................................................................................................................... 35 deselect ................................................................................................................................................. 36 no operation ......................................................................................................................................... 36 load mode register ............................................................................................................................. 36 active ...................................................................................................................................................... 36 read ......................................................................................................................................................... 37 write ....................................................................................................................................................... 38 precharge .............................................................................................................................................. 39 burst terminate ................................................................................................................................... 40 auto refresh ......................................................................................................................................... 40 self refresh ........................................................................................................................................... 41 deep power-down ................................................................................................................................. 41 truth tables ................................................................................................................................................... 42 state diagram ................................................................................................................................................ 47 initialization .................................................................................................................................................. 48 standard mode register .................................................................................................................................. 51 burst length .............................................................................................................................................. 52 burst type .................................................................................................................................................. 52 cas latency ............................................................................................................................................... 53 operating mode ......................................................................................................................................... 54 extended mode register ................................................................................................................................. 55 temperature-compensated self refresh ...................................................................................................... 55 partial-array self refresh ............................................................................................................................ 56 output drive strength ................................................................................................................................ 56 status read register ....................................................................................................................................... 57 bank/row activation ...................................................................................................................................... 59 read operation ............................................................................................................................................. 60 write operation ........................................................................................................................................... 71 precharge operation .................................................................................................................................. 83 auto precharge ............................................................................................................................................... 83 concurrent auto precharge ......................................................................................................................... 84 auto refresh operation ............................................................................................................................. 89 self refresh operation ............................................................................................................................... 90 power-down .................................................................................................................................................. 91 deep power-down ..................................................................................................................................... 93 clock change frequency ................................................................................................................................ 95 revision history ............................................................................................................................................. 96 rev. h C 06/13 ............................................................................................................................................. 96 rev. g C 10/11 ............................................................................................................................................. 96 rev. f C 10/11 ............................................................................................................................................. 96 512mb: x16, x32 mobile lpddr sdram features pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
rev. e C 6/11 ............................................................................................................................................... 96 rev. d C 4/11 .............................................................................................................................................. 96 rev. c C 1/11 ............................................................................................................................................... 96 rev. b C 02/10 ............................................................................................................................................. 96 rev. a C 01/10 ............................................................................................................................................. 96 512mb: x16, x32 mobile lpddr sdram features pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
list of figures figure 1: 512mb mobile lpddr part numbering .............................................................................................. 2 figure 2: functional block diagram (x16) ......................................................................................................... 9 figure 3: functional block diagram (x32) ....................................................................................................... 10 figure 4: 60-ball vfbga C top view, x16 only .................................................................................................. 11 figure 5: 90-ball vfbga C top view, x32 only .................................................................................................. 12 figure 6: 60-ball vfbga (8mm x 9mm), package code: bf .............................................................................. 15 figure 7: 90-ball vfbga (8mm x 13mm), package code: b5 ............................................................................. 16 figure 8: typical self refresh current vs. temperature .................................................................................... 25 figure 9: active command .......................................................................................................................... 37 figure 10: read command ........................................................................................................................... 38 figure 11: write command ......................................................................................................................... 39 figure 12: precharge command ................................................................................................................ 40 figure 13: deep power-down command ................................................................................................... 41 figure 14: simplified state diagram ............................................................................................................... 47 figure 15: initialize and load mode registers ................................................................................................. 49 figure 16: alternate initialization with cke low ............................................................................................ 50 figure 17: standard mode register definition ................................................................................................. 51 figure 18: cas latency .................................................................................................................................. 54 figure 19: extended mode register ................................................................................................................ 55 figure 20: status read register timing ........................................................................................................... 57 figure 21: status register definition .............................................................................................................. 58 figure 22: read burst ................................................................................................................................... 61 figure 23: consecutive read bursts .............................................................................................................. 62 figure 24: nonconsecutive read bursts ........................................................................................................ 63 figure 25: random read accesses .................................................................................................................. 64 figure 26: terminating a read burst ............................................................................................................. 65 figure 27: read-to-write ............................................................................................................................ 66 figure 28: read-to-precharge .................................................................................................................. 67 figure 29: data output timing C t dqsq, t qh, and data valid window (x16) .................................................... 68 figure 30: data output timing C t dqsq, t qh, and data valid window (x32) .................................................... 69 figure 31: data output timing C t ac and t dqsck .......................................................................................... 70 figure 32: data input timing ......................................................................................................................... 72 figure 33: write C dm operation .................................................................................................................... 73 figure 34: write burst ................................................................................................................................. 74 figure 35: consecutive write-to-write ....................................................................................................... 75 figure 36: nonconsecutive write-to-write ................................................................................................. 75 figure 37: random write cycles .................................................................................................................. 76 figure 38: write-to-read C uninterrupting ................................................................................................. 77 figure 39: write-to-read C interrupting ...................................................................................................... 78 figure 40: write-to-read C odd number of data, interrupting ..................................................................... 79 figure 41: write-to-precharge C uninterrupting ....................................................................................... 80 figure 42: write-to-precharge C interrupting ........................................................................................... 81 figure 43: write-to-precharge C odd number of data, interrupting .......................................................... 82 figure 44: bank read C with auto precharge ................................................................................................... 85 figure 45: bank read C without auto precharge .............................................................................................. 86 figure 46: bank write C with auto precharge .................................................................................................. 87 figure 47: bank write C without auto precharge ............................................................................................. 88 figure 48: auto refresh mode ........................................................................................................................ 89 figure 49: self refresh mode .......................................................................................................................... 91 figure 50: power-down entry (in active or precharge mode) ........................................................................... 92 512mb: x16, x32 mobile lpddr sdram features pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 51: power-down mode (active or precharge) ........................................................................................ 93 figure 52: deep power-down mode ............................................................................................................... 94 figure 53: clock stop mode ........................................................................................................................... 95 512mb: x16, x32 mobile lpddr sdram features pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
list of tables table 1: key timing parameters (cl = 3) ........................................................................................................... 1 table 2: configuration addressing ................................................................................................................... 2 table 3: ball descriptions .............................................................................................................................. 13 table 4: absolute maximum ratings .............................................................................................................. 17 table 5: ac/dc electrical characteristics and operating conditions ............................................................... 17 table 6: capacitance (x16, x32) ...................................................................................................................... 19 table 7: i dd specifications and conditions, C40c to +85c (x16) ..................................................................... 20 table 8: i dd specifications and conditions, C40c to +85c (x32) ..................................................................... 21 table 9: i dd specifications and conditions, C40c to +105c (x16) ................................................................... 22 table 10: i dd specifications and conditions, C40c to +105c (x32) .................................................................. 23 table 11: i dd6 specifications and conditions .................................................................................................. 24 table 12: electrical characteristics and recommended ac operating conditions ............................................ 26 table 13: target output drive characteristics (full strength) ........................................................................... 31 table 14: target output drive characteristics (three-quarter strength) .......................................................... 32 table 15: target output drive characteristics (one-half strength) .................................................................. 33 table 16: truth table C commands ................................................................................................................ 35 table 17: dm operation truth table .............................................................................................................. 36 table 18: truth table C current state bank n C command to bank n ................................................................ 42 table 19: truth table C current state bank n C command to bank m ............................................................... 44 table 20: truth table C cke ........................................................................................................................... 46 table 21: burst definition table ..................................................................................................................... 52 512mb: x16, x32 mobile lpddr sdram features pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
general description the 512mb mobile low-power ddr sdram is a high-speed cmos, dynamic random- access memory containing 536,870,912 bits. it is internally configured as a quad-bank dram. each of the x16s 134,217,728-bit banks is organized as 8192 rows by 1024 col- umns by 16 bits. each of the x32s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits. in the reduced page-size (lg) option, each of the x32s 134,217,728- bit banks are organized as 16,384 rows by 256 columns by 32 bits. note: 1. throughout this data sheet, various figures and text refer to dqs as dq. dq should be interpreted as any and all dq collectively, unless specifically stated otherwise. addi- tionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. for the lower byte (dq[7:0]), dm refers to ldm and dqs refers to ldqs. for the upper byte (dq[15:8]), dm refers to udm and dqs refers to udqs. the x32 is divided into 4 bytes. for dq[7:0], dm refers to dm0 and dqs refers to dqs0. for dq[15:8], dm refers to dm1 and dqs refers to dqs1. for dq[23:16], dm refers to dm2 and dqs refers to dqs2. for dq[31:24], dm refers to dm3 and dqs refers to dqs3. 2. complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all require- ments. 3. any specific requirement takes precedence over a general statement. 512mb: x16, x32 mobile lpddr sdram general description pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
functional block diagrams figure 2: functional block diagram (x16) row- address mux control logic column- address counter/ latch standard mode register extended mode register command decode address ba0, ba1 cke ck# ck cs# we# cas# ras# address register i/o gating dm mask logic column decoder bank 0 memory array bank 0 row- address latch and decoder bank control logic bank 1 bank 2 bank 3 refresh counter 16 16 16 2 input registers 2 2 2 2 rcvrs 2 32 32 2 2 4 32 ck out data dqs mask data ck ck in drvrs mux dqs generator 16 16 16 16 16 32 dq[15:0] ldqs, udqs 2 read latch write fifo and drivers 1 col 0 col 0 sense amplifiers ldm, udm ck 512mb: x16, x32 mobile lpddr sdram functional block diagrams pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 3: functional block diagram (x32) ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch standard mode register extended mode register command decode address, ba0, ba1 cke address register i/o gating dm mask logic bank 0 memory array bank 0 row- address latch and decoder bank control logic bank 1 bank 2 bank 3 refresh counter 32 2 2 32 32 2 input registers 4 4 4 4 rcvrs 4 64 64 8 64 ck out data dqs mask data ck ck in drvrs mux dqs generator 32 32 32 32 32 64 dq[31:0] dqs0 dqs1 dqs2 dqs3 4 read latch write fifo and drivers 1 col 0 col 0 sense amplifiers dm0 dm1 dm2 dm3 ck column decoder 512mb: x16, x32 mobile lpddr sdram functional block diagrams pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
ball assignments figure 4: 60-ball vfbga C top view, x16 only 1 2 3 4 6 7 8 9 5 a b c d e f g h j k v ssq dq14 dq12 dq10 dq8 nc ck# a12 a8 a5 v ss v ddq v ssq v ddq v ssq v ss cke a9 a6 v ss dq15 dq13 dq11 dq9 udqs udm ck a11 a7 a4 v ddq dq1 dq3 dq5 dq7 a13 we# cs# a10/ap a2 dq0 dq2 dq4 dq6 ldqs ldm cas# ba0 a0 a3 v dd v ssq v ddq v ddq v dd ras# ba1 a1 v dd test 1 notes: 1. d9 is a test pin that must be tied to v ss or v ssq in normal operations. 2. unused address pins become rfu. 512mb: x16, x32 mobile lpddr sdram ball assignments pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 5: 90-ball vfbga C top view, x32 only v ssq dq30 dq28 dq26 dq24 nc ck# a12 a8 a5 dq8 dq10 dq12 dq14 v ssq v ss v ddq v ssq v ddq v ssq v dd cke a9 a6 a4 v ssq v ddq v ssq v ddq v ss dq31 dq29 dq27 dq25 dqs3 dm3 ck a11 a7 dm1 dqs1 dq9 dq11 dq13 dq15 v ddq dq17 dq19 dq21 dq23 a13 we# cs# a10 /ap a2 dq7 dq5 dq3 dq1 v ddq dq16 dq18 dq20 dq22 dqs2 dm2 cas# ba0 a0 dm0 dqs0 dq6 dq4 dq2 dq0 v dd v ssq v ddq v ddq v ss ras# ba1 a1 a3 v ddq v ssq v ddq v ssq v dd 1 2 3 4 6 7 8 9 5 a b c d e f g h j k l m n p r test 1 notes: 1. d9 is a test pin that must be tied to v ss or v ssq in normal operations. 2. unused address pins become rfu. 512mb: x16, x32 mobile lpddr sdram ball assignments pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
ball descriptions the ball descriptions table is a comprehensive list of all possible balls for all supported packages. not all balls listed are supported for a given package. table 3: ball descriptions symbol type description ck, ck# input clock: ck is the system clock input. ck and ck# are differential clock inputs. all ad- dress and control input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. input and output data is referenced to the crossing of ck and ck# (both directions of the crossing). cke cke0, cke1 input clock enable: cke high activates, and cke low deactivates, the internal clock signals, input buffers, and output drivers. taking cke low enables precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except self refresh exit. all input buffers (except cke) are disabled during power-down and self refresh modes. cke0 is used for a single lpddr product. cke1 is used for dual lpddr products and is considered rfu for single lpddr mcps. cs# cs0#, cs1# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for ex- ternal bank selection on systems with multiple banks. cs# is considered part of the command code. cs0# is used for a single lpddr product. cs1# is used for dual lpddr products and is considered rfu for single lpddr mcps. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. udm, ldm (x16) dm[3:0] (x32) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs balls. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode reg- ister is loaded during a load mode register command. a[13:0] input address inputs: provide the row address for active commands, and the column ad- dress and auto precharge bit (a10) for read or write commands, to select one loca- tion out of the memory array in the respective bank. during a precharge command, a10 determines whether the precharge applies to one bank (a10 low, bank selec- ted by ba0, ba1) or all banks (a10 high). the address inputs also provide the op-code during a load mode register command. the maximum address range is dependent upon configuration. unused address balls become rfu. test input test pin: must be tied to v ss or v ssq in normal operations. dq[15:0] (x16) dq[31:0] (x32) input/ output data input/output: data bus for x16 and x32. ldqs, udqs (x16) dqs[3:0] (x32) input/ output data strobe: output with read data, input with write data. dqs is edge-aligned with read data, center-aligned in write data. it is used to capture data. tq output temperature sensor output: tq high when lpddr t j exceeds 85c. v ddq supply dq power supply. 512mb: x16, x32 mobile lpddr sdram ball descriptions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 3: ball descriptions (continued) symbol type description v ssq supply dq ground. v dd supply power supply. v ss supply ground. nc C no connect: may be left unconnected. rfu C reserved for future use. balls marked rfu may or may not be connected internally. these balls should not be used. contact factory for details. 512mb: x16, x32 mobile lpddr sdram ball descriptions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
package dimensions figure 6: 60-ball vfbga (8mm x 9mm), package code: bf seating plane ball a1 id 0.275 min 0.9 0.1 6.4 ctr 8 0.1 0.8 typ 9 0.1 0.8 typ 7.2 ctr 60x ? 0.45 dimensions apply to solder balls post-reflow on ? 0.40 smd ball pads. solder ball material: sac105 (98.5% sn, 1% ag, 0.5% cu). ball a1 id (covered by sr) 1 2 3 7 8 9 a 0.12 a a b c d e f g h j k note: 1. all dimensions are in millimeters. 512mb: x16, x32 mobile lpddr sdram package dimensions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 7: 90-ball vfbga (8mm x 13mm), package code: b5 seating plane 0.12 a ball a1 id a 0.275 min 0.9 0.1 6.4 ctr 8 0.1 0.8 typ 13 0.1 0.8 typ 11.2 ctr 90x ?0.45 dimensions apply to solder balls post-reflow on ?0.40 smd ball pads. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu) or sac105 (98.5% sn, 1% ag, 0.5% cu). ball a1 id (covered by sr) a b c d e f g h j k l m n p r 1 2 3 7 8 9 note: 1. all dimensions are in millimeters. 512mb: x16, x32 mobile lpddr sdram package dimensions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 4: absolute maximum ratings note 1 applies to all parameters in this table parameter symbol min max unit v dd /v ddq supply voltage relative to v ss v dd /v ddq C1.0 2.4 v voltage on any pin relative to v ss v in C0.5 2.4 or (v ddq + 0.3v), whichever is less v storage temperature (plastic) t stg C55 150 ?c note: 1. v dd and v ddq must be within 300mv of each other at all times. v ddq must not exceed v dd . table 5: ac/dc electrical characteristics and operating conditions notes 1C5 apply to all parameters/conditions in this table; v dd /v ddq = 1.70C1.95v parameter/condition symbol min max unit notes supply voltage v dd 1.70 1.95 v 6, 7 i/o supply voltage v ddq 1.70 1.95 v 6, 7 address and command inputs input voltage high v ih 0.8 v ddq v ddq + 0.3 v 8, 9 input voltage low v il C0.3 0.2 v ddq v 8, 9 clock inputs (ck, ck#) dc input voltage v in C0.3 v ddq + 0.3 v 10 dc input differential voltage v id(dc) 0.4 v ddq v ddq + 0.6 v 10, 11 ac input differential voltage v id(ac) 0.6 v ddq v ddq + 0.6 v 10, 11 ac differential crossing voltage v ix 0.4 v ddq 0.6 v ddq v 10, 12 data inputs dc input high voltage v ih(dc) 0.7 v ddq v ddq + 0.3 v 8, 9, 13 dc input low voltage v il(dc) C0.3 0.3 v ddq v 8, 9, 13 ac input high voltage v ih(ac) 0.8 v ddq v ddq + 0.3 v 8, 9, 13 ac input low voltage v il(ac) C0.3 0.2 v ddq v 8, 9, 13 data outputs dc output high voltage: logic 1 (i oh = C0.1ma) v oh 0.9 v ddq C v dc output low voltage: logic 0 (i ol = 0.1ma) v ol C 0.1 v ddq v leakage current input leakage current any input 0v v in v dd (all other pins not under test = 0v) i i C1 1 a 512mb: x16, x32 mobile lpddr sdram electrical specifications pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 5: ac/dc electrical characteristics and operating conditions (continued) notes 1C5 apply to all parameters/conditions in this table; v dd /v ddq = 1.70C1.95v parameter/condition symbol min max unit notes output leakage current (dq are disabled; 0v v out v ddq ) i oz C5 5 a operating temperature commercial t a 0 +70 ?c industrial t a C40 +85 ?c automotive t a C40 +105 ?c notes: 1. all voltages referenced to v ss . 2. all parameters assume proper device initialization. 3. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. outputs measured with equivalent load; transmission line delay is assumed to be very small: i/o 20pf i/o 10pf full drive strength half drive strength 50 50 5. timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ddq /2 (or to the crossing point for ck/ck#). the output timing reference voltage level is v ddq /2. 6. any positive glitch must be less than one-third of the clock cycle and not more than +200mv or 2.0v, whichever is less. any negative glitch must be less than one-third of the clock cycle and not exceed either C150mv or +1.6v, whichever is more positive. 7. v dd and v ddq must track each other and v ddq must be less than or equal to v dd . 8. to maintain a valid level, the transitioning edge of the input must: 8a. sustain a constant slew rate from the current ac level through to the target ac lev- el, v il(ac) or v ih(ac) . 8b. reach at least the target ac level. 8c. after the ac target level is reached, continue to maintain at least the target dc lev- el, v il(dc) or v ih(dc) . 9. v ih overshoot: v ihmax = v ddq + 1.0v for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v ilmin = C1.0v for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate. 10. ck and ck# input slew rate must be 1 v/ns (2 v/ns if measured differentially). 11. v id is the magnitude of the difference between the input level on ck and the input lev- el on ck#. 12. the value of v ix is expected to equal v ddq/2 of the transmitting device and must track variations in the dc level of the same. 13. dq and dm input slew rates must not deviate from dqs by more than 10%. 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if slew rate exceeds 4 v/ns, functionality is uncertain. 512mb: x16, x32 mobile lpddr sdram electrical specifications pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 6: capacitance (x16, x32) note 1 applies to all the parameters in this table parameter symbol min max unit notes input capacitance: ck, ck# c ck 1.5 3.0 pf delta input capacitance: ck, ck# c dck C 0.25 pf 2 input capacitance: command and address c i 1.5 3.0 pf delta input capacitance: command and address c di C 0.5 pf 2 input/output capacitance: dq, dqs, dm c io 2.0 4.5 pf delta input/output capacitance: dq, dqs, dm c dio C 0.5 pf 3 notes: 1. this parameter is sampled. v dd /v ddq = 1.70C1.95v, f = 100 mhz, t a = 25?c, v out(dc) = v ddq/2 , v out (peak-to-peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 2. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. the i/o capacitance per dqs and dq byte/group will not differ by more than this maxi- mum amount for any given device. 512mb: x16, x32 mobile lpddr sdram electrical specifications pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications C i dd parameters table 7: i dd specifications and conditions, C40c to +85c (x16) notes 1C5 apply to all the parameters/conditions in this table; v dd /v ddq = 1.70C1.95v parameter/condition symbol max unit notes -5 -54 -6 -75 operating 1 bank active precharge current: t rc = t rc (min); t ck = t ck (min); cke is high; cs is high between valid commands; address inputs are switching every 2 clock cycles; data bus in- puts are stable i dd0 70 65 60 50 ma 6 precharge power-down standby current: all banks idle; cke is low; cs is high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2p 300 300 300 300 a 7, 8 precharge power-down standby current: clock stopped; all banks idle; cke is low; cs is high; ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ps 300 300 300 300 a 7 precharge nonpower-down standby current: all banks idle; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2n 15 15 15 12 ma 9 precharge nonpower-down standby current: clock stopped; all banks idle; cke = high; cs = high; ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ns 8 8 8 8 ma 9 active power-down standby current: 1 bank active; cke = low; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd3p 3 3 3 3 ma 8 active power-down standby current: clock stopped; 1 bank ac- tive; cke = low; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ps 2 2 2 2 ma active nonpower-down standby: 1 bank active; cke = high; cs = high; t ck = t ck (min); address and control inputs are switch- ing; data bus inputs are stable i dd3n 15 15 15 15 ma 6 active nonpower-down standby: clock stopped; 1 bank active; cke = high; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ns 8 8 8 8 ma 6 operating burst read: 1 bank active; bl = 4; t ck = t ck (min); continuous read bursts; iout = 0ma; address inputs are switching every 2 clock cycles; 50% data changing each burst i dd4r 115 110 105 100 ma 6 operating burst write: 1 bank active; bl = 4; t ck = t ck (min); continuous write bursts; address inputs are switching; 50% data changing each burst i dd4w 115 110 105 100 ma 6 auto refresh: burst refresh; cke = high; ad- dress and control inputs are switching; data bus inputs are stable t rfc = 138ns i dd5 95 95 95 95 ma 10 t rfc = t refi i dd5a 3 3 3 3 ma 10, 11 deep power-down current: address and control balls are sta- ble; data bus inputs are stable i dd8 10 10 10 10 a 7, 13 512mb: x16, x32 mobile lpddr sdram electrical specifications C i dd parameters pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 8: i dd specifications and conditions, C40c to +85c (x32) notes 1C5 apply to all the parameters/conditions in this table; v dd /v ddq = 1.70C1.95v parameter/condition symbol max unit notes -5 -54 -6 -75 operating 1 bank active precharge current: t rc = t rc (min); t ck = t ck (min); cke is high; cs is high between valid commands; address inputs are switching every 2 clock cycles; data bus inputs are stable jedec-standard option i dd0 70 65 60 50 ma 6 reduced page size option i dd0 70 65 60 50 ma 6 precharge power-down standby current: all banks idle; cke is low; cs is high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2p 300 300 300 300 a 7, 8 precharge power-down standby current: clock stopped; all banks idle; cke is low; cs is high, ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ps 300 300 300 300 a 7 precharge nonpower-down standby current: all banks idle; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2n 15 15 15 12 ma 9 precharge nonpower-down standby current: clock stopped; all banks idle; cke = high; cs = high; ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ns 8 8 8 8 ma 9 active power-down standby current: 1 bank active; cke = low; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd3p 3 3 3 3 ma 8 active power-down standby current: clock stopped; 1 bank ac- tive; cke = low; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ps 2 2 2 2 ma active nonpower-down standby: 1 bank active; cke = high; cs = high; t ck = t ck (min); address and control inputs are switch- ing; data bus inputs are stable i dd3n 15 15 15 15 ma 6 active nonpower-down standby: clock stopped; 1 bank active; cke = high; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ns 8 8 8 8 ma 6 operating burst read: 1 bank active; bl = 4; cl = 3; t ck = t ck (min); continuous read bursts; iout = 0ma; address inputs are switching every 2 clock cycles; 50% data changing each burst i dd4r 115 110 105 100 ma 6 operating burst write: one bank active; bl = 4; t ck = t ck (min); continuous write bursts; address inputs are switching; 50% data changing each burst i dd4w 115 110 105 100 ma 6 auto refresh: burst refresh; cke = high; ad- dress and control inputs are switching; data bus inputs are stable t rfc = 138ns i dd5 95 95 95 95 ma 10 t rfc = t refi i dd5a 3 3 3 3 ma 10, 11 deep power-down current: address and control pins are stable; data bus inputs are stable i dd8 10 10 10 10 a 7, 13 512mb: x16, x32 mobile lpddr sdram electrical specifications C i dd parameters pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 9: i dd specifications and conditions, C40c to +105c (x16) notes 1C5 apply to all the parameters/conditions in this table; v dd /v ddq = 1.70C1.95v parameter/condition symbol max unit notes -5 -54 -6 -75 operating 1 bank active precharge current: t rc = t rc (min); t ck = t ck (min); cke is high; cs is high between valid commands; address inputs are switching every 2 clock cycles; data bus in- puts are stable i dd0 70 65 60 50 ma 6 precharge power-down standby current: all banks idle; cke is low; cs is high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2p 600 600 600 600 a 7, 8 precharge power-down standby current: clock stopped; all banks idle; cke is low; cs is high; ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ps 600 600 600 600 a 7 precharge nonpower-down standby current: all banks idle; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2n 16 16 16 13 ma 9 precharge nonpower-down standby current: clock stopped; all banks idle; cke = high; cs = high; ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ns 9 9 9 9 ma 9 active power-down standby current: 1 bank active; cke = low; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd3p 4 4 4 4 ma 8 active power-down standby current: clock stopped; 1 bank ac- tive; cke = low; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ps 3 3 3 3 ma active nonpower-down standby: 1 bank active; cke = high; cs = high; t ck = t ck (min); address and control inputs are switch- ing; data bus inputs are stable i dd3n 16 16 16 16 ma 6 active nonpower-down standby: clock stopped; 1 bank active; cke = high; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ns 9 9 9 9 ma 6 operating burst read: 1 bank active; bl = 4; t ck = t ck (min); continuous read bursts; iout = 0ma; address inputs are switching every 2 clock cycles; 50% data changing each burst i dd4r 115 110 105 100 ma 6 operating burst write: 1 bank active; bl = 4; t ck = t ck (min); continuous write bursts; address inputs are switching; 50% data changing each burst i dd4w 115 110 105 100 ma 6 auto refresh: burst refresh; cke = high; ad- dress and control inputs are switching; data bus inputs are stable t rfc = 138ns i dd5 95 95 95 95 ma 10 t rfc = t refi i dd5a 8 8 8 8 ma 10, 11 deep power-down current: address and control balls are sta- ble; data bus inputs are stable i dd8 15 15 15 15 a 7, 13 512mb: x16, x32 mobile lpddr sdram electrical specifications C i dd parameters pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 10: i dd specifications and conditions, C40c to +105c (x32) notes 1C5 apply to all the parameters/conditions in this table; v dd /v ddq = 1.70C1.95v parameter/condition symbol max unit notes -5 -54 -6 -75 operating 1 bank active precharge current: t rc = t rc (min); t ck = t ck (min); cke is high; cs is high between valid commands; address inputs are switching every 2 clock cycles; data bus inputs are stable jedec-standard option i dd0 70 65 60 50 ma 6 reduced page size option i dd0 70 65 60 50 ma 6 precharge power-down standby current: all banks idle; cke is low; cs is high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2p 600 600 600 600 a 7, 8 precharge power-down standby current: clock stopped; all banks idle; cke is low; cs is high, ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ps 600 600 600 600 a 7 precharge nonpower-down standby current: all banks idle; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd2n 16 16 16 13 ma 9 precharge nonpower-down standby current: clock stopped; all banks idle; cke = high; cs = high; ck = low, ck# = high; ad- dress and control inputs are switching; data bus inputs are sta- ble i dd2ns 9 9 9 9 ma 9 active power-down standby current: 1 bank active; cke = low; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd3p 4 4 4 4 ma 8 active power-down standby current: clock stopped; 1 bank ac- tive; cke = low; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ps 3 3 3 3 ma active nonpower-down standby: 1 bank active; cke = high; cs = high; t ck = t ck (min); address and control inputs are switch- ing; data bus inputs are stable i dd3n 16 16 16 16 ma 6 active nonpower-down standby: clock stopped; 1 bank active; cke = high; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd3ns 9 9 9 9 ma 6 operating burst read: 1 bank active; bl = 4; cl = 3; t ck = t ck (min); continuous read bursts; iout = 0ma; address inputs are switching every 2 clock cycles; 50% data changing each burst i dd4r 115 110 105 100 ma 6 operating burst write: one bank active; bl = 4; t ck = t ck (min); continuous write bursts; address inputs are switching; 50% data changing each burst i dd4w 115 110 105 100 ma 6 auto refresh: burst refresh; cke = high; ad- dress and control inputs are switching; data bus inputs are stable t rfc = 138ns i dd5 95 95 95 95 ma 10 t rfc = t refi i dd5a 8 8 8 8 ma 10, 11 deep power-down current: address and control pins are stable; data bus inputs are stable i dd8 15 15 15 15 a 7, 13 512mb: x16, x32 mobile lpddr sdram electrical specifications C i dd parameters pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 11: i dd6 specifications and conditions notes 1C5, 7, and 12 apply to all the parameters/conditions in this table; v dd /v ddq = 1.70C 1.95v parameter/condition symbol standard unit self refresh cke = low; t ck = t ck (min); address and control inputs are stable; data bus inputs are stable full array, 105?c i dd6 n/a 14 a full array, 85c 700 a full array, 45?c 390 a 1/2 array, 85?c 520 a 1/2 array, 45?c 310 a 1/4 array, 85?c 430 a 1/4 array, 45?c 275 a 1/8 array, 85?c 430 a 1/8 array, 45?c 275 a 1/16 array, 85?c 375 a 1/16 array, 45?c 250 a notes: 1. all voltages referenced to v ss . 2. tests for i dd characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ddq/2 (or to the crossing point for ck/ck#). the output timing reference voltage level is v ddq/2 . 4. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time with the outputs open. 5. i dd specifications are tested after the device is properly initialized and values are aver- aged at the defined cycle rate. 6. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t rasmax for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras. 7. measurement is taken 500ms after entering into this operating mode to provide settling time for the tester. 8. v dd must not vary more than 4% if cke is not active while any bank is active. 9. i dd2n specifies dq, dqs, and dm to be driven to a valid high or low logic level. 10. cke must be active (high) during the entire time a refresh command is executed. from the time the auto refresh command is registered, cke must be active at each rising clock edge until t rfc later. 11. this limit is a nominal value and does not result in a fail. cke is high during refresh command period ( t rfc (min)) else cke is low (for example, during standby). 12. values for i dd6 85?c are guaranteed for the entire temperature range. all other i dd6 val- ues are estimated. 13. typical values at 25?c, not a maximum value. 14. self refresh is not supported for at (85c to 105c) operation. 512mb: x16, x32 mobile lpddr sdram electrical specifications C i dd parameters pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 8: typical self refresh current vs. temperature 0 50 100 150 200 250 300 350 400 450 500 C40 0 25 45 60 75 85 90 i dd6 (a) full half quarter eighth sixteenth 512mb: x16, x32 mobile lpddr sdram electrical specifications C i dd parameters pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications C ac operating conditions table 12: electrical characteristics and recommended ac operating conditions notes 1C9 apply to all the parameters in this table; v dd /v ddq = 1.70C1.95v parameter symbol -5 -54 -6 -75 unit notes min max min max min max min max access window of dq from ck/ck# cl = 3 t ac 2.0 5.0 2.0 5.0 2.0 5.0 2.0 6.0 ns cl = 2 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5 clock cycle time cl = 3 t ck 5.0 C 5.4 C 6 C 7.5 C ns 10 cl = 2 12 C 12 C 12 C 12 C ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck cke minimum pulse width (high and low) t cke 1 C 1 C 1 C 1 C t ck 11 auto precharge write recovery + precharge time t dal C C C C C C C C C 12 dq and dm input hold time relative to dqs (fast slew rate) t dh f 0.48 C 0.54 C 0.6 C 0.8 C ns 13, 14, 15 dq and dm input hold time relative to dqs (slow slew rate) t dh s 0.58 C 0.64 C 0.7 C 0.9 C ns dq and dm input setup time relative to dqs (fast slew rate) t ds f 0.48 C 0.54 C 0.6 C 0.8 C ns 13, 14, 15 dq and dm input setup time relative to dqs (slow slew rate) t ds s 0.58 C 0.64 C 0.7 C 0.9 C ns dq and dm input pulse width (for each input) t dipw 1.8 C 1.9 C 2.1 C 1.8 C ns 16 access window of dqs from ck/ck# cl = 3 t dqsck 2.0 5.0 2.0 5.0 2.0 5.0 2.0 6.0 ns cl = 2 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5 ns dqs input high pulse width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs input low pulse width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqsCdq skew, dqs to last dq valid, per group, per access t dqsq C 0.4 C 0.45 C 0.45 C 0.6 ns 13, 17 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge from ck rising C hold time t dsh 0.2 C 0.2 C 0.2 C 0.2 C t ck dqs falling edge to ck rising C setup time t dss 0.2 C 0.2 C 0.2 C 0.2 C t ck 512mb: x16, x32 mobile lpddr sdram electrical specifications C ac operating conditions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 12: electrical characteristics and recommended ac operating conditions (continued) notes 1C9 apply to all the parameters in this table; v dd /v ddq = 1.70C1.95v parameter symbol -5 -54 -6 -75 unit notes min max min max min max min max data valid output window (dvw) n/a t qh - t dqsq t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 17 half-clock period t hp t ch, t cl C t ch, t cl C t ch, t cl C t ch, t cl C ns 18 data-out high-z window from ck/ck# cl = 3 t hz C 5.0 C 5.0 C 5.0 C 6.0 ns 19, 20 cl = 2 C 6.5 C 6.5 C 6.5 C 6.5 ns data-out low-z window from ck/ck# t lz 1.0 C 1.0 C 1.0 C 1.0 C ns 19 address and control input hold time (fast slew rate) t ih f 0.9 C 1.0 C 1.1 C 1.3 C ns 15, 21 address and control input hold time (slow slew rate) t ih s 1.1 C 1.2 C 1.3 C 1.5 C ns address and control input setup time (fast slew rate) t is f 0.9 C 1.0 C 1.1 C 1.3 C ns 15, 21 address and control input setup time (slow slew rate) t is s 1.1 C 1.2 C 1.3 C 1.5 C ns address and control input pulse width t ipw 2.3 C 2.5 C 2.6 C t is + t ih C ns 16 load mode register command cycle time t mrd 2 C 2 C 2 C 2 C t ck dqCdqs hold, dqs to first dq to go nonvalid, per access t qh t hp - t qhs C t hp - t qhs C t hp - t qhs C t hp - t qhs C ns 13, 17 data hold skew factor t qhs C 0.5 C 0.5 C 0.65 C 0.75 ns active-to-precharge command t ras 40 70,000 42 70,000 42 70,000 45 70,000 ns 22 active to active/active to auto refresh command period t rc 55 C 58.2 C 60 C 67.5 C ns 23 active to read or write delay t rcd 15 C 16.2 C 18 C 22.5 C ns refresh period t ref C 64 C 64 C 64 C 64 ms 24 average periodic refresh interval: 64mb, 128mb, and 256mb (x32) t refi C 15.6 C 15.6 C 15.6 C 15.6 s 24 average periodic refresh interval: 256mb, 512mb, 1gb, 2gb t refi C 7.8 C 7.8 C 7.8 C 7.8 s 24 auto refresh command period t rfc 72 C 72 C 72 C 72 C ns 512mb: x16, x32 mobile lpddr sdram electrical specifications C ac operating conditions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 12: electrical characteristics and recommended ac operating conditions (continued) notes 1C9 apply to all the parameters in this table; v dd /v ddq = 1.70C1.95v parameter symbol -5 -54 -6 -75 unit notes min max min max min max min max precharge command period t rp 15 C 16.2 C 18 C 22.5 C ns dqs read preamble cl = 3 t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck cl = 2 t rpre 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 10 C 10.8 C 12 C 15 C ns read of srr to next valid command t src cl + 1 C cl + 1 C cl + 1 C cl + 1 C t ck srr to read t srr 2 C 2 C 2 C 2 C t ck internal temperature sen- sor valid temperature out- put enable t tq 2 C 2 C 2 C 2 C ms dqs write preamble t wpre 0.25 C 0.25 C 0.25 C 0.25 C t ck dqs write preamble setup time t wpres 0 C 0 C 0 C 0 C ns 25, 26 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 27 write recovery time t wr 15 C 15 C 15 C 15 C ns 28 internal write-to-read command delay t wtr 2 C 2 C 1 C 1 C t ck exit power-down mode to first valid command t xp 2 C 2 C 1 C 1 C t ck exit self refresh to first valid command t xsr 112.5 C 112.5 C 112.5 C 112.5 C ns 29 notes: 1. all voltages referenced to v ss . 2. all parameters assume proper device initialization. 3. tests for ac timing and electrical ac and dc characteristics may be conducted at nomi- nal supply voltage levels, but the related specifications and device operation are guar- anteed for the full voltage ranges specified. 4. the circuit shown below represents the timing reference load used in defining the rele- vant timing parameters of the device. it is not intended to be either a precise represen- tation of the typical system environment or a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to system environment. specifications are correlated to pro- duction test conditions (generally a coaxial transmission line terminated at the tester electronics). for the half-strength driver with a nominal 10pf load, parameters t ac and t qh are expected to be in the same range. however, these parameters are not subject to production test but are estimated by design/characterization. use of ibis or other simu- 512mb: x16, x32 mobile lpddr sdram electrical specifications C ac operating conditions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
lation tools for system design validation is suggested. i/o 20pf i/o 10pf full drive strength half drive strength 50 50 5. the ck/ck# input reference voltage level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference voltage level for signals other than ck/ck# is v ddq/2 . 6. a ck and ck# input slew rate 1 v/ns (2 v/ns if measured differentially) is assumed for all parameters. 7. all ac timings assume an input slew rate of 1 v/ns. 8. cas latency definition: with cl = 2, the first data element is valid at ( t ck + t ac) after the clock at which the read command was registered; for cl = 3, the first data element is valid at (2 t ck + t ac) after the first clock at which the read command was registered. 9. timing tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ddq/2 or to the crossing point for ck/ck#. the output tim- ing reference voltage level is v ddq/2 . 10. clock frequency change is only permitted during clock stop, power-down, or self refresh mode. 11. in cases where the device is in self refresh mode for t cke, t cke starts at the rising edge of the clock and ends when cke transitions high. 12. t dal = ( t wr/ t ck) + ( t rp/ t ck): for each term, if not already an integer, round up to the next highest integer. 13. referenced to each output group: for x16, ldqs with dq[7:0]; and udqs with dq[15:8]. for x32, dqs0 with dq[7:0]; dqs1 with dq[15:8]; dqs2 with dq[23:16]; and dqs3 with dq[31:24]. 14. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 1.0 v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if the slew rate exceeds 4 v/ns, functionality is uncertain. 15. the transition time for input signals (cas#, cke, cs#, dm, dq, dqs, ras#, we#, and ad- dresses) are measured between v il(dc) to v ih(ac) for rising input signals and v ih(dc) to v il(ac) for falling input signals. 16. these parameters guarantee device timing but are not tested on each device. 17. the valid data window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t hp - t qhs). the data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. the clock is provided a maximum duty cycle variation of 45/55. functionality is uncertain when operating be- yond a 45/55 ratio. 18. t hp (min) is the lesser of t cl (min) and t ch (min) actually applied to the device ck and ck# inputs, collectively. 19. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 20. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 21. fast command/address input slew rate 1 v/ns. slow command/address input slew rate 0.5 v/ns. if the slew rate is less than 0.5 v/ns, timing must be derated: t is has an addi- tional 50ps per each 100 mv/ns reduction in slew rate from the 0.5 v/ns. t ih has 0ps add- ed, therefore, it remains constant. if the slew rate exceeds 4.5 v/ns, functionality is un- certain. 22. reads and writes with auto precharge must not be issued until t ras (min) can be satis- fied prior to the internal precharge command being issued. 512mb: x16, x32 mobile lpddr sdram electrical specifications C ac operating conditions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
23. dram devices should be evenly addressed when being accessed. disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime. 24. for the automotive temperature parts, t ref = t ref/2 and t refi = t refi/2. 25. this is not a device limit. the device will operate with a negative value, but system per- formance could be degraded due to bus turnaround. 26. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 27. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will de- grade accordingly. 28. at least 1 clock cycle is required during t wr time when in auto precharge mode. 29. clock must be toggled a minimum of two times during the t xsr period. 512mb: x16, x32 mobile lpddr sdram electrical specifications C ac operating conditions pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
output drive characteristics table 13: target output drive characteristics (full strength) notes 1C2 apply to all values; characteristics are specified under best and worst process variations/conditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 2.80 18.53 C2.80 C18.53 0.20 5.60 26.80 C5.60 C26.80 0.30 8.40 32.80 C8.40 C32.80 0.40 11.20 37.05 C11.20 C37.05 0.50 14.00 40.00 C14.00 C40.00 0.60 16.80 42.50 C16.80 C42.50 0.70 19.60 44.57 C19.60 C44.57 0.80 22.40 46.50 C22.40 C46.50 0.85 23.80 47.48 C23.80 C47.48 0.90 23.80 48.50 C23.80 C48.50 0.95 23.80 49.40 C23.80 C49.40 1.00 23.80 50.05 C23.80 C50.05 1.10 23.80 51.35 C23.80 C51.35 1.20 23.80 52.65 C23.80 C52.65 1.30 23.80 53.95 C23.80 C53.95 1.40 23.80 55.25 C23.80 C55.25 1.50 23.80 56.55 C23.80 C56.55 1.60 23.80 57.85 C23.80 C57.85 1.70 23.80 59.15 C23.80 C59.15 1.80 C 60.45 C C60.45 1.90 C 61.75 C C61.75 notes: 1. based on nominal impedance of 25 (full strength) at v ddq /2. 2. the full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the i-v curves. 512mb: x16, x32 mobile lpddr sdram output drive characteristics pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 14: target output drive characteristics (three-quarter strength) notes 1C3 apply to all values; characteristics are specified under best and worst process variations/conditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 1.96 12.97 C1.96 C12.97 0.20 3.92 18.76 C3.92 C18.76 0.30 5.88 22.96 C5.88 C22.96 0.40 7.84 25.94 C7.84 C25.94 0.50 9.80 28.00 C9.80 C28.00 0.60 11.76 29.75 C11.76 C29.75 0.70 13.72 31.20 C13.72 C31.20 0.80 15.68 32.55 C15.68 C32.55 0.85 16.66 33.24 C16.66 C33.24 0.90 16.66 33.95 C16.66 C33.95 0.95 16.66 34.58 C16.66 C34.58 1.00 16.66 35.04 C16.66 C35.04 1.10 16.66 35.95 C16.66 C35.95 1.20 16.66 36.86 C16.66 C36.86 1.30 16.66 37.77 C16.66 C37.77 1.40 16.66 38.68 C16.66 C38.68 1.50 16.66 39.59 C16.66 C39.59 1.60 16.66 40.50 C16.66 C40.50 1.70 16.66 41.41 C16.66 C41.41 1.80 C 42.32 C C42.32 1.90 C 43.23 C C43.23 notes: 1. based on nominal impedance of 37 (three-quarter drive strength) at v ddq /2. 2. the full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the i-v curves. 3. contact factory for availability of three-quarter drive strength. 512mb: x16, x32 mobile lpddr sdram output drive characteristics pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 15: target output drive characteristics (one-half strength) notes 1C3 apply to all values; characteristics are specified under best and worst process variations/conditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 1.27 8.42 C1.27 C8.42 0.20 2.55 12.30 C2.55 C12.30 0.30 3.82 14.95 C3.82 C14.95 0.40 5.09 16.84 C5.09 C16.84 0.50 6.36 18.20 C6.36 C18.20 0.60 7.64 19.30 C7.64 C19.30 0.70 8.91 20.30 C8.91 C20.30 0.80 10.16 21.20 C10.16 C21.20 0.85 10.80 21.60 C10.80 C21.60 0.90 10.80 22.00 C10.80 C22.00 0.95 10.80 22.45 C10.80 C22.45 1.00 10.80 22.73 C10.80 C22.73 1.10 10.80 23.21 C10.80 C23.21 1.20 10.80 23.67 C10.80 C23.67 1.30 10.80 24.14 C10.80 C24.14 1.40 10.80 24.61 C10.80 C24.61 1.50 10.80 25.08 C10.80 C25.08 1.60 10.80 25.54 C10.80 C25.54 1.70 10.80 26.01 C10.80 C26.01 1.80 C 26.48 C C26.48 1.90 C 26.95 C C26.95 notes: 1. based on nominal impedance of 55 (one-half drive strength) at v ddq /2. 2. the full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the i-v curves. 3. the i-v curve for one-quarter drive strength is approximately 50% of one-half drive strength. 512mb: x16, x32 mobile lpddr sdram output drive characteristics pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
functional description the mobile lpddr sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o. single read or write access for the device consists of a single 2 n -bit-wide, one-clock-cycle data transfer at the internal dram core and two corresponding n -bit-wide, one-half-clock- cycle data transfers at the i/o. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the device during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 device has two data strobes, one for the lower byte and one for the upper byte; the x32 device has four data strobes, one per byte. the lpddr device operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. com- mands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the device are burst-oriented; accesses start at a selected lo- cation and continue for a programmed number of locations in a programmed se- quence. accesses begin with the registration of an active command, followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits regis- tered coincident with the read or write command are used to select the starting col- umn location for the burst access. the device provides for programmable read or write burst lengths of 2, 4, 8, or 16. an auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdram, the pipelined, multibank architecture of lpddr sup- ports concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. deep power-down mode is offered to achieve maximum power reduction by eliminating the power of the memory array. data will not be retained after the device enters deep pow- er-down mode. two self refresh features, temperature-compensated self refresh (tcsr) and partial-ar- ray self refresh (pasr), offer additional power savings. tcsr is controlled by the auto- matic on-chip temperature sensor. pasr can be customized using the extended mode register settings. the two features can be combined to achieve even greater power sav- ings. the dll that is typically used on standard ddr devices is not necessary on lpddr de- vices. it has been omitted to save power. 512mb: x16, x32 mobile lpddr sdram functional description pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
commands a quick reference for available commands is provided in table 16 and table 17 (page 36), followed by a written description of each command. three additional truth tables (table 18 (page 42), table 19 (page 44), and table 20 (page 46)) provide cke commands and current/next state information. table 16: truth table C commands cke is high for all commands shown except self refresh and deep power-down; all states and sequences not shown are reserved and/or illegal name (function) cs# ras# cas# we# address notes deselect (nop) h x x x x 1 no operation (nop) l h h h x 1 active (select bank and activate row) l l h h bank/row 2 read (select bank and column, and start read burst) l h l h bank/column 3 write (select bank and column, and start write burst) l h l l bank/column 3 burst terminate or deep power-down (enter deep power-down mode) l h h l x 4, 5 precharge (deactivate row in bank or banks) l l h l code 6 auto refresh (refresh all or single bank) or self re- fresh (enter self refresh mode) l l l h x 7, 8 load mode register l l l l op-code 9 notes: 1. deselect and nop are functionally interchangeable. 2. ba0Cba1 provide bank address and a[0: i ] provide row address (where i = the most sig- nificant address bit for each configuration). 3. ba0Cba1 provide bank address; a[0: i ] provide column address (where i = the most sig- nificant address bit for each configuration); a10 high enables the auto precharge fea- ture (nonpersistent); a10 low disables the auto precharge feature. 4. applies only to read bursts with auto precharge disabled; this command is undefined and should not be used for read bursts with auto precharge enabled and for write bursts. 5. this command is a burst terminate if cke is high and deep power-down if cke is low. 6. a10 low: ba0Cba1 determine which bank is precharged. a10 high: all banks are precharged and ba0Cba1 are dont care. 7. this command is auto refresh if cke is high, self refresh if cke is low. 8. internal refresh counter controls row addressing; in self refresh mode all inputs and i/os are dont care except for cke. 9. ba0Cba1 select the standard mode register, extended mode register, or status register. 512mb: x16, x32 mobile lpddr sdram commands pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 17: dm operation truth table name (function) dm dq notes write enable l valid 1, 2 write inhibit h x 1, 2 notes: 1. used to mask write data; provided coincident with the corresponding data. 2. all states and sequences not shown are reserved and/or illegal. deselect the deselect function (cs# high) prevents new commands from being executed by the device. operations already in progress are not affected. no operation the no operation (nop) command is used to instruct the selected device to perform a nop. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a[0: n ]. see mode register descriptions in standard mode register and extended mode register. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to activate a row in a particular bank for a subsequent access. the values on the ba0 and ba1 inputs select the bank, and the address provided on inputs a[0: n ] selects the row. this row remains active for accesses until a pre- charge command is issued to that bank. a precharge command must be issued be- fore opening a different row in the same bank. 512mb: x16, x32 mobile lpddr sdram commands pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 9: active command cs# we# cas# ras# cke address row high ba0, ba1 bank ck ck# dont care read the read command is used to initiate a burst read access to an active row. the values on the ba0 and ba1 inputs select the bank; the address provided on inputs a[ i :0] (where i = the most significant column address bit for each configuration) selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. 512mb: x16, x32 mobile lpddr sdram commands pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 10: read command cs# we# cas# ras# cke column address a10 ba0, ba1 high en ap dis ap bank ck ck# dont care note: 1. en ap = enable auto precharge; dis ap = disable auto precharge. write the write command is used to initiate a burst write access to an active row. the values on the ba0 and ba1 inputs select the bank; the address provided on inputs a[ i :0] (where i = the most significant column address bit for each configuration) selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array, subject to the dm input logic level appearing coincident with the data. if a given dm signal is regis- tered low, the corresponding data will be written to memory; if the dm signal is regis- tered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. if a write or a read is in progress, the entire data burst must be complete prior to stopping the clock (see clock change frequency (page 95)). a burst completion for writes is defined when the write postamble and t wr or t wtr are satisfied. 512mb: x16, x32 mobile lpddr sdram commands pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 11: write command cs# we# cas# ras# cke column a10 ba0, ba1 high en ap dis ap bank ck ck# dont care address note: 1. en ap = enable auto precharge; dis ap = disable auto precharge. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks will be precharged, and in the case where only one bank is pre- charged, inputs ba0 and ba1 select the bank. otherwise, ba0 and ba1 are treated as dont care. after a bank has been precharged, it is in the idle state and must be acti- vated prior to any read or write commands being issued to that bank. 512mb: x16, x32 mobile lpddr sdram commands pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 12: precharge command cs# we# cas# ras# cke a10 ba0, ba1 high all banks single bank bank ck ck# dont care address note: 1. if a10 is high, bank address becomes dont care. burst terminate the burst terminate command is used to truncate read bursts with auto pre- charge disabled. the most recently registered read command prior to the burst ter- minate command will be truncated, as described in read operation. the open page from which the read was terminated remains open. auto refresh auto refresh is used during normal operation of the device and is analogous to cas#-before-ras# (cbr) refresh in fpm/edo dram. the auto refresh com- mand is nonpersistent and must be issued each time a refresh is required. addressing is generated by the internal refresh controller. this makes the address bits a dont care during an auto refresh command. for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. the auto refresh period begins when the auto refresh command is registered and ends t rfc later. 512mb: x16, x32 mobile lpddr sdram commands pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
self refresh the self refresh command is used to place the device in self refresh mode; self re- fresh mode is used to retain data in the memory device while the rest of the system is powered down. when in self refresh mode, the device retains data without external clocking. the self refresh command is initiated like an auto refresh command, except that cke is disabled (low). after the self refresh command is registered, all inputs to the device become dont care with the exception of cke, which must re- main low. micron recommends that, prior to self refresh entry and immediately upon self refresh exit, the user perform a burst auto refresh cycle for the number of refresh rows. alterna- tively, if a distributed refresh pattern is used, this pattern should be immediately re- sumed upon self refresh exit. deep power-down the deep power-down (dpd) command is used to enter dpd mode, which achieves maximum power reduction by eliminating the power to the memory array. data will not be retained when the device enters dpd mode. the dpd command is the same as a burst terminate command with cke low. figure 13: deep power-down command cs# we# cas# ras# cke address ba0, ba1 ck ck# dont care 512mb: x16, x32 mobile lpddr sdram commands pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
truth tables table 18: truth table C current state bank n C command to bank n notes 1C6 apply to all parameters in this table current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle l l h h active (select and activate row) l l l h auto refresh 7 l l l l load mode register 7 row active l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto pre- charge disabled) l h l h read (select column and start new read burst) 10 l h l l write (select column and start write burst) 10, 12 l l h l precharge (truncate read burst, start precharge) 8 l h h l burst terminate 9 write (auto pre- charge disabled) l h l h read (select column and start read burst) 10, 11 l h l l write (select column and start new write burst) 10 l l h l precharge (truncate write burst, start precharge) 8, 11 notes: 1. this table applies when cke n - 1 was high, cke n is high and after t xsr has been met (if the previous state was self refresh), after t xp has been met (if the previous state was power-down), or after a full initialization (if the previous state was deep power-down). 2. this table is bank-specific, except where noted (for example, the current state is for a specific bank and the commands shown are supported for that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated with auto precharge disabled and has not yet ter- minated or been terminated. write: a write burst has been initiated with auto precharge disabled and has not yet terminated or been terminated. 4. the states listed below must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or supported commands to the other bank, must be issued on any clock edge occurring during these states. supported commands to any other bank are determined by that banks current state. precharging: starts with registration of a precharge command and ends when t rp is met. after t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. 512mb: x16, x32 mobile lpddr sdram truth tables pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read with auto-precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write with auto-precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. 5. the states listed below must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. after t rfc is met, the device will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. after t mrd is met, the device will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks need to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking. 12. a write command can be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. 512mb: x16, x32 mobile lpddr sdram truth tables pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 19: truth table C current state bank n C command to bank m notes 1C6 apply to all parameters in this table current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle x x x x any command supported to bank m row activating, active, or pre- charging l l h h active (select and activate row) l h l h read (select column and start read burst) l h l l write (select column and start write burst) l l h l precharge read (auto pre- charge disabled) l l h h active (select and activate row) l h l h read (select column and start new read burst) l h l l write (select column and start write burst) 7 l l h l precharge write (auto pre- charge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) l h l l write (select column and start new write burst) l l h l precharge read (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) l h l l write (select column and start write burst) 7 l l h l precharge write (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) l h l l write (select column and start new write burst) l l h l precharge notes: 1. this table applies when cke n - 1 was high, cke n is high and after t xsr has been met (if the previous state was self refresh), after t xp has been met (if the previous state was power-down) or after a full initialization (if the previous state was deep power-down). 2. this table describes alternate bank operation, except where noted (for example, the cur- rent state is for bank n and the commands shown are those supported for issue to bank m , assuming that bank m is in such a state that the given command is supported). excep- tions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated and has not yet terminated or been terminated. write: a write burst has been initiated and has not yet terminated or been terminated. 3a. both the read with auto precharge enabled state or the write with auto precharge enabled state can be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was 512mb: x16, x32 mobile lpddr sdram truth tables pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the command and ends when the precharge period (or t rp) begins. this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is supported, as long as that com- mand does not interrupt the read or write data transfer already in process. in either case, all other related limitations apply (i.e., contention between read data and write data must be avoided). 3b. the minimum delay from a read or write command (with auto precharge enabled) to a command to a different bank is summarized below. from command to command minimum delay (with concurrent auto precharge) write with auto precharge read or read with auto precharge write or write with auto pre- charge precharge active [1 + (bl/2)] t ck + t wtr (bl/2) t ck 1 t ck 1 t ck read with auto precharge read or read with auto precharge write or write with auto pre- charge precharge active (bl/2) t ck [cl + (bl/2)] t ck 1 t ck 1 t ck 4. auto refresh and load mode register commands can only be issued when all banks are idle. 5. all states and sequences not shown are illegal or reserved. 6. requires appropriate dm masking. 7. a write command can be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. 512mb: x16, x32 mobile lpddr sdram truth tables pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 20: truth table C cke notes 1C4 apply to all parameters in this table current state cke n - 1 cke n command n action n notes active power-down l l x maintain active power-down deep power-down l l x maintain deep power-down precharge power-down l l x maintain precharge power-down self refresh l l x maintain self refresh active power-down l h deselect or nop exit active power-down 5 deep power-down l h deselect or nop exit deep power-down 6 precharge power-down l h deselect or nop exit precharge power-down self refresh l h deselect or nop exit self refresh 5, 7 bank(s) active h l deselect or nop active power-down entry all banks idle h l burst terminate deep power-down entry all banks idle h l deselect or nop precharge power-down entry all banks idle h l auto refresh self refresh entry h h see table 19 (page 44) h h see table 19 (page 44) notes: 1. cke n is the logic state of cke at clock edge n ; cke n - 1 was the state of cke at the previ- ous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. deselect or nop commands should be issued on each clock edge occurring during the t xp or t xsr period. 6. after exiting deep power-down mode, a full dram initialization sequence is required. 7. the clock must toggle at least two times during the t xsr period. 512mb: x16, x32 mobile lpddr sdram truth tables pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
state diagram figure 14: simplified state diagram power on power applied sref lmr aref srefx act ckel ckel ckeh ckeh pre preall lmr emr deep power- down self refresh idle: all banks precharged row active burst terminate reading reading automatic sequence command sequence writing write write writing write a precharging active power- down precharge power- down auto refresh pre write a read a read a pre pre read a read read bst dpd dpdx read srr srr read read pre lmr act = active dpdx = exit deep power-down read a = read w/ auto precharge aref = auto refresh emr = load extended mode register sref = enter self refresh bst = burst terminate lmr = load mode register srefx = exit self refresh ckeh = exit power-down pre = precharge srr = status register read ckel = enter power-down preall = precharge all banks write = write w/o auto precharge dpd = enter deep power-down read = read w/o auto precharge write a = write w/ auto precharge write write a 512mb: x16, x32 mobile lpddr sdram state diagram pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
initialization prior to normal operation, the device must be powered up and initialized in a prede- fined manner. using initialization procedures other than those specified will result in undefined operation. if there is an interruption to the device power, the device must be re-initialized using the initialization sequence described below to ensure proper functionality of the device. to properly initialize the device, this sequence must be followed: 1. the core power (v dd ) and i/o power (v ddq ) must be brought up simultaneously. it is recommended that v dd and v ddq be from the same power source, or v ddq must never exceed v dd . standard initialization requires that cke be asserted high (see figure 15 (page 49)). alternatively, initialization can be completed with cke low provided that cke transitions high t is prior to t0 (see figure 16 (page 50)). 2. when power supply voltages are stable and the cke has been driven high, it is safe to apply the clock. 3. when the clock is stable, a 200 s minimum delay is required by the mobile lpddr prior to applying an executable command. during this time, nop or deselect commands must be issued on the command bus. 4. issue a precharge all command. 5. issue nop or deselect commands for at least t rp time. 6. issue an auto refresh command followed by nop or deselect commands for at least t rfc time. issue a second auto refresh command followed by nop or deselect commands for at least t rfc time. two auto refresh commands must be issued. typically, both of these commands are issued at this stage as de- scribed above. 7. using the load mode register command, load the standard mode register as desired. 8. issue nop or deselect commands for at least t mrd time. 9. using the load mode register command, load the extended mode register to the desired operating modes. note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. issue nop or deselect commands for at least t mrd time. after steps 1C10 are completed, the device has been properly initialized and is ready to receive any valid command. 512mb: x16, x32 mobile lpddr sdram initialization pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 15: initialize and load mode registers cke lvcmos high level dq ba0, ba1 load standard mode register load extended mode register t mrd 4 t mrd 4 t rfc 4 t rfc 4 powe r -up: v dd and ck stable t = 200s high-z dm dqs high-z address row a10 row ck ck# v dd v ddq t ch t cl t ck command 1 lmr nop lmr t is t ih ba0 = l, ba1 = l ba0 = l, ba1 = h op-code op-code t is t ih t is t ih t is t ih t is t ih op-code op-code pre all banks t0 t1 t a 0 tb0 t c 0 td0 t e 0 tf0 dont care bank ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp 4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 2 ar ar ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) act 3 notes: 1. pre = precharge command; lmr = load mode register command; ar = auto re- fresh command; act = active command. 2. nop or deselect commands are required for at least 200 s. 3. other valid commands are possible. 4. nops or deselects are required during this time. 512mb: x16, x32 mobile lpddr sdram initialization pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 16: alternate initialization with cke low cke lvcmos low level ck ck# v dd v ddq command 1 lmr lmr t is t is t ch t cl t ih pre t0 t1 t a 0 tb0 t c 0 td0 t e 0 tf0 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 2 ar ar nop 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) act 3 ( ) ( ) ( ) ( ) power up: v dd and ck stable t = 200s nop dont care notes: 1. pre = precharge command; lmr = load mode register command; ar = auto re- fresh command; act = active command. 2. nop or deselect commands are required for at least 200 s. 3. other valid commands are possible. 512mb: x16, x32 mobile lpddr sdram initialization pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
standard mode register the standard mode register bit definition enables the selection of burst length, burst type, cas latency (cl), and operating mode, as shown in figure 17. reserved states should not be used as this may result in setting the device into an unknown state or cause incompatibility with future versions of lpddr devices. the standard mode regis- ter is programmed via the load mode register command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again, until the device goes into deep power-down mode, or until the device loses power. reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait t mrd before initiating the subse- quent operation. violating any of these requirements will result in unspecified opera- tion. figure 17: standard mode register definition m3 = 0 reserved 2 4 8 16 reserved reserved reserved m3 = 1 reserved 2 4 8 16 reserved reserved reserved m3 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 standard mode register (mx) address bus 9 7 6 5 4 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 operating mode a10 an ... ba0 ba1 10 ... n 0 n + 1 n + 2 mn 0 C m10 0 C m9 0 C m8 0 C operating mode normal operation all other states reserved 0 0 1 1 mode register definition standard mode register status register extended mode register reserved m n + 2 0 1 0 1 m n + 1 m7 0 C ... note: 1. the integer n is equal to the most significant address bit. 512mb: x16, x32 mobile lpddr sdram standard mode register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
burst length read and write accesses to the device are burst-oriented, and the burst length (bl) is programmable. the burst length determines the maximum number of column loca- tions that can be accessed for a given read or write command. burst lengths of 2, 4, 8, or 16 locations are available for both sequential and interleaved burst types. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap when a boundary is reached. the block is uniquely se- lected by a[ i :1] when bl = 2, by a[ i :2] when bl = 4, by a[ i :3] when bl = 8, and by a[ i :4] when bl = 16, where a i is the most significant column address bit for a given configura- tion. the remaining (least significant) address bits are used to specify the starting loca- tion within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst can be programmed to be either sequential or interleaved via the standard mode register. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. table 21: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 0 0-1 0-1 1 1-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 16 a3 a2 a1 a0 512mb: x16, x32 mobile lpddr sdram standard mode register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 21: burst definition table (continued) burst length starting column address order of accesses within a burst type = sequential type = interleaved 0 0 0 0 0-1-2-3-4-5-6-7-8-9-a-b-c-d-e-f 0-1-2-3-4-5-6-7-8-9-a-b-c-d-e-f 0 0 0 1 1-2-3-4-5-6-7-8-9-a-b-c-d-e-f-0 1-0-3-2-5-4-7-6-9-8-b-a-d-c-f-e 0 0 1 0 2-3-4-5-6-7-8-9-a-b-c-d-e-f-0-1 2-3-0-1-6-7-4-5-a-b-8-9-e-f-c-d 0 0 1 1 3-4-5-6-7-8-9-a-b-c-d-e-f-0-1-2 3-2-1-0-7-6-5-4-b-a-9-8-f-e-d-c 0 1 0 0 4-5-6-7-8-9-a-b-c-d-e-f-0-1-2-3 4-5-6-7-0-1-2-3-c-d-e-f-8-9-a-b 0 1 0 1 5-6-7-8-9-a-b-c-d-e-f-0-1-2-3-4 5-4-7-6-1-0-3-2-d-c-f-e-9-8-b-a 0 1 1 0 6-7-8-9-a-b-c-d-e-f-0-1-2-3-4-5 6-7-4-5-2-3-0-1-e-f-c-d-a-b-8-9 0 1 1 1 7-8-9-a-b-c-d-e-f-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-f-e-d-c-b-a-9-8 1 0 0 0 8-9-a-b-c-d-e-f-0-1-2-3-4-5-6-7 8-9-a-b-c-d-e-f-0-1-2-3-4-5-6-7 1 0 0 1 9-a-b-c-d-e-f-0-1-2-3-4-5-6-7-8 9-8-b-a-d-c-f-e-1-0-3-2-5-4-7-6 1 0 1 0 a-b-c-d-e-f-0-1-2-3-4-5-6-7-8-9 a-b-8-9-e-f-c-d-2-3-0-1-6-7-4-5 1 0 1 1 b-c-d-e-f-0-1-2-3-4-5-6-7-8-9-a b-a-9-8-f-e-d-c-3-2-1-0-7-6-5-4 1 1 0 0 c-d-e-f-0-1-2-3-4-5-6-7-8-9-a-b c-d-e-f-8-9-a-b-4-5-6-7-0-1-2-3 1 1 0 1 d-e-f-0-1-2-3-4-5-6-7-8-9-a-b-c d-c-f-e-9-8-b-a-5-4-7-6-1-0-3-2 1 1 1 0 e-f-0-1-2-3-4-5-6-7-8-9-a-b-c-d e-f-c-d-a-b-8-9-6-7-4-5-2-3-0-1 1 1 1 1 f-0-1-2-3-4-5-6-7-8-9-a-b-c-d-e f-e-d-c-b-a-9-8-7-6-5-4-3-2-1-0 cas latency the cas latency (cl) is the delay, in clock cycles, between the registration of a read command and the availability of the first output data. the latency can be set to 2 or 3 clocks, as shown in figure 18 (page 54). for cl = 3, if the read command is registered at clock edge n , then the data will be nominally available at ( n + 2 clocks + t ac). for cl = 2, if the read command is regis- tered at clock edge n , then the data will be nominally available at ( n + 1 clock + t ac). 512mb: x16, x32 mobile lpddr sdram standard mode register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 18: cas latency ck ck# ck ck# t0 t1 t2 t2n t3 t3n t1n command dq dqs cl = 2 t0 t1 t2 t2n t3 t3n dont care transitioning data read nop nop nop command dq dqs cl = 3 read nop nop nop d out n d out n + 1 d out n + 3 d out n + 2 d out n d out n + 1 cl - 1 t ac cl - 1 t ac operating mode the normal operating mode is selected by issuing a load mode register command with bits a[ n :7] each set to zero, and bits a[6:0] set to the desired values. all other combinations of values for a[ n :7] are reserved for future use. reserved states should not be used because unknown operation or incompatibility with future versions may result. 512mb: x16, x32 mobile lpddr sdram standard mode register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
extended mode register the emr controls additional functions beyond those set by the mode registers. these additional functions include drive strength, tcsr, and pasr. the emr is programmed via the load mode register command with ba0 = 0 and ba1 = 1. information in the emr will be retained until it is programmed again, the de- vice goes into deep power-down mode, or the device loses power. figure 19: extended mode register extended mode register (ex) address bus 9 7 6 5 4 3 8 2 1 pasr tcsr 1 ds operation 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 10 ... e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 partial-array self refresh coverage full array 1/2 array 1/4 array reserved reserved 1/8 array 1/16 array reserved ba0 ... ba1 1 n n + 1 n + 2 0 e10 0 C ... 0 C en 0 C e9 0 e8 0 C normal ar operation all other states reserved a n e6 0 0 1 1 0 0 1 1 e7 0 0 0 0 1 1 1 1 e5 0 1 0 1 0 1 0 1 drive strength full strength 1/2 strength 1/4 strength 3/4 strength 3/4 strength reserved reserved reserved e7Ce0 valid C C en + 2 0 0 1 1 en + 1 0 1 0 1 mode register definition standard mode register status register extended mode register reserved notes: 1. on-die temperature sensor is used in place of tcsr. setting these bits will have no ef- fect. 2. the integer n is equal to the most significant address bit. temperature-compensated self refresh this device includes a temperature sensor that is implemented for automatic control of the self refresh oscillator. programming the temperature-compensated self refresh (tcsr) bits will have no effect on the device. the self refresh oscillator will continue to refresh at the optimal factory-programmed rate for the device temperature. 512mb: x16, x32 mobile lpddr sdram extended mode register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
partial-array self refresh for further power savings during self refresh, the partial-array self refresh (pasr) feature enables the controller to select the amount of memory to be refreshed during self re- fresh. the refresh options include: ? full array: banks 0, 1, 2, and 3 ? one-half array: banks 0 and 1 ? one-quarter array: bank 0 ? one-eighth array: bank 0 with row address most significant bit (msb) = 0 ? one-sixteenth array: bank 0 with row address msb = 0 and row address msb - 1 = 0 read and write commands can still be issued to the full array during standard opera- tion, but only the selected regions of the array will be refreshed during self refresh. data in regions that are not selected will be lost. output drive strength because the device is designed for use in smaller systems that are typically point-to- point connections, an option to control the drive strength of the output buffers is provi- ded. drive strength should be selected based on the expected loading of the memory bus. the output driver settings are 25 , 37 , and 55 internal impedance for full, three- quarter, and one-half drive strengths, respectively. 512mb: x16, x32 mobile lpddr sdram extended mode register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
status read register the status read register (srr) is used to read the manufacturer id, revision id, refresh multiplier, width type, and density of the device, as shown in figure 21 (page 58). the srr is read via the load mode register command with ba0 = 1 and ba1 = 0. the sequence to perform an srr command is as follows: 1. the device must be properly initialized and in the idle or all banks precharged state. 2. issue a load mode register command with ba[1:0] = 01 and all address pins set to 0. 3. wait t srr; only nop or deselect commands are supported during the t srr time. 4. issue a read command. 5. subsequent commands to the device must be issued t src after the srr read command is issued; only nop or deselect commands are supported during t src. srr output is read with a burst length of 2. srr data is driven to the outputs on the first bit of the burst, with the output being dont care on the second bit of the burst. figure 20: status read register timing command ba0, ba1 ck ck# address read nop nop t0 t1 t2 t3 t4 t5 t6 dont care nop dqs dq srr out 4 t rp t srr t src pre 1 lmr nop 2 nop valid t8 ba0 = 1 ba1 = 0 0 note 5 cl = 3 3 transitioning data notes: 1. all banks must be idle prior to status register read. 2. nop or deselect commands are required between the lmr and read commands ( t srr), and between the read and the next valid command ( t src). 3. cas latency is predetermined by the programming of the mode register. cl = 3 is shown as an example only. 4. burst length is fixed to 2 for srr regardless of the value programmed by the mode reg- ister. 5. the second bit of the data-out burst is a dont care. 512mb: x16, x32 mobile lpddr sdram status read register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 21: status register definition status register i/o bus (clk l->h edge) 9 7 6 5 4 3 8 2 1 manufacturer id reserved revision id refresh rate s12 dq11 s11 dq10 s10 dq9 s9 dq8 s8 dq7 s7 dq6 s6 dq5 s5 dq4 s4 dq3 s3 dq2 s2 dq1 s1 dq0 s0 10 11 12 s2 s1 manufacturer id reserved samsung infineon elpida reserved reserved dq14 dq12 s14 dq31...dq16 s31..s16 reserved 1 13 14 31..16 0 s13 s3 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 reserved reserved winbond reserved reserved reserved reserved micron esmt nvm s0 width type density dq13 15 dq15 s15 s6 s5 revision id the manufacturers revision number starts at 0000 and increments by 0001 each time a change in the specification (ac timings or feature set), ibis (pull- up or pull-down characteristics), or process occurs. x x x x 0 0 0 0 s4 ... ... ... ... s10 s9 refresh multiplier 2 reserved reserved 2x 1x reserved 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0.25x s8 s7 device width 32 bits 1 0 s11 16 bits device type lpddr2 1 0 s12 lpddr s15 s14 density 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 s13 2gb reserved reserved reserved 1gb 512mb 256mb 128mb reserved notes: 1. reserved bits should be set to 0 for future compatibility. 2. refresh multiplier is based on the memory device on-board temperature sensor. re- quired average periodic refresh interval = t refi multiplier. 512mb: x16, x32 mobile lpddr sdram status read register pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
bank/row activation before any read or write commands can be issued to a bank within the device, a row in that bank must be opened. this is accomplished via the active command, which selects both the bank and the row to be activated (see the active command figure). after a row is opened with the active command, a read or write command can be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been precharged. the minimum time interval between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. the mini- mum time interval between successive active commands to different banks is defined by t rrd. 512mb: x16, x32 mobile lpddr sdram bank/row activation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
read operation read burst operations are initiated with a read command, as shown in figure 10 (page 38). the starting column and bank addresses are provided with the read com- mand, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cl after the read command. each subsequent data-out ele- ment will be valid nominally at the next positive or negative clock edge. figure 22 (page 61) shows general timing for each possible cl setting. dqs is driven by the device along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. the read burst is considered complete when the read postamble is satisfied. upon completion of a burst, assuming no other commands have been initiated, the dq will go to high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid data window is depicted in figure 29 (page 68) and fig- ure 30 (page 69). a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is depicted in figure 31 (page 70). data from any read burst can be truncated by a read or write command to the same or alternate bank, by a burst terminate command, or by a precharge com- mand to the same bank, provided that the auto precharge mode was not activated. data from any read burst can be concatenated with or truncated with data from a sub- sequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). this is shown in figure 23 (page 62). a read command can be initiated on any clock cycle following a previous read com- mand. nonconsecutive read data is shown in figure 24 (page 63). full-speed random read accesses within a page (or pages) can be performed as shown in figure 25 (page 64). data from any read burst can be truncated with a burst terminate command, as shown in figure 26 (page 65). the burst terminate latency is equal to the read (cas) latency; for example, the burst terminate command should be issued x cy- cles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure 27 (page 66). a read burst can be followed by, or truncated with, a precharge command to the same bank, provided that auto pre- charge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs. this is shown in figure 28 (page 67). following the precharge command, a subsequent 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
command to the same bank cannot be issued until t rp is met. part of the row precharge time is hidden during the access of the last data elements. figure 22: read burst nop nop d out n 1 d out n + 1 nop nop nop read bank a, col n t0 t1 t1n t2 t2n t3 t3n t4 t5 d out n + 2 d out n + 3 ck# ck command address dqs dq cl = 2 nop nop nop nop nop read bank a, col n t0 t1 t2 t2n t3 t3n t4 t5 ck# ck command address dqs dq cl = 3 dont care transitioning data d out n d out n + 1 d out n + 2 d out n + 3 notes: 1. d out n = data-out from column n . 2. bl = 4. 3. shown with nominal t ac, t dqsck, and t dqsq. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 23: consecutive read bursts ck ck# ck ck# t0 t1 t2 t3 t2n t3n t4 t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t5 t4n t5n command read nop read nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b dont care transitioning data dq dqs cl = 2 dq dqs cl = 3 d out n 1 d out n + 1 d out n + 3 d out n + 2 d out b d out b + 1 d out b + 3 d out b + 2 d out n d out n + 1 d out n + 3 d out n + 2 d out b d out b + 1 notes: 1. d out n (or b ) = data-out from column n (or column b ). 2. bl = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first). 3. shown with nominal t ac, t dqsck, and t dqsq. 4. example applies only when read commands are issued to same device. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 24: nonconsecutive read bursts ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t6 ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t6 command read nop nop nop nop nop address bank, col n read bank, col b dont care transitioning data dq dqs cl = 2 cl = 2 command read nop nop nop nop nop address bank, col n read bank, col b dq dqs cl = 3 cl = 3 d out n d out n + 1 d out n + 3 d out n + 2 d out n 1 d out b d out n + 1 d out n + 3 d out n + 2 d out b d out b + 1 d out b + 2 notes: 1. d out n (or b ) = data-out from column n (or column b ). 2. bl = 4, 8, or 16 (if burst is 8 or 16, the second burst interrupts the first). 3. shown with nominal t ac, t dqsck, and t dqsq. 4. example applies when read commands are issued to different devices or nonconsecu- tive reads. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 25: random read accesses ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n command read read read nop nop address bank, col n bank, col x bank, col b bank, col x bank, col b read bank, col g command address read read read nop nop bank, col n read bank, col g dont care transitioning data dq dqs cl = 2 dq dqs cl = 3 d out n 1 d out n + 1 d out x + 1 d out x d out b d out b + 1 d out g + 1 d out g d out n d out n + 1 d out b d out b + 1 d out x + 1 d out x notes: 1. d out n (or x , b , g ) = data-out from column n ( or column x , column b , column g ). 2. bl = 2, 4, 8, or 16 (if 4, 8, or 16, the following burst interrupts the previous). 3. reads are to an active row in any bank. 4. shown with nominal t ac, t dqsck, and t dqsq. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 26: terminating a read burst ck ck# t0 t1 t2 t3 t2n t4 t5 t1n ck ck# t0 t1 t2 t3 t2n t4 t5 t3n command read 1 bst 2 nop nop nop nop address bank a, col n dont care transitioning data dq 3 dqs cl = 2 command read 1 bst 2 nop nop nop nop address dq 3 dqs cl = 3 d out n d out n + 1 d out n d out n + 1 bank a, col n notes: 1. bl = 4, 8, or 16. 2. bst = burst terminate command; page remains open. 3. d out n = data-out from column n . 4. shown with nominal t ac, t dqsck, and t dqsq. 5. cke = high. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 27: read-to-write ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n ck dont care transitioning data command read 1 bst 2 nop nop nop address bank, col n write 1 bank, col b dm t dqss (nom) dq 3,4 dqs cl = 2 command read 1 bst 2 nop nop address bank, col n write 1 bank, col b dm t dqss (nom) dq 3,4 dqs cl = 3 nop d out n d out n + 1 d in b + 1 d in b d out n d out n + 1 d in b+1 d in b+2 d in b+3 d in b notes: 1. bl = 4 in the cases shown (applies for bursts of 8 and 16 as well; if bl = 2, the bst com- mand shown can be nop). 2. bst = burst terminate command; page remains open. 3. d out n = data-out from column n . 4. d in b = data-in from column b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. cke = high. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 28: read-to-precharge ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n command read 1 nop pre 2 nop nop act 3 address banka, col n bank a, (a or all) bank a, row banka, col n bank a, (a or all) bank a, row dq 4 dqs cl = 2 t rp read 1 nop pre 2 nop nop act 3 command address dq 4 dqs cl = 3 t rp dont care transitioning data d out n d out n + 1 d out n + 3 d out n + 2 d out n d out n + 1 d out n + 3 d out n + 2 notes: 1. bl = 4, or an interrupted burst of 8 or 16. 2. pre = precharge command. 3. act = active command. 4. d out n = data-out from column n . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. read-to-precharge equals 2 clocks, which enables 2 data pairs of data-out. 7. a read command with auto precharge enabled, provided t ras (min) is met, would cause a precharge to be performed at x number of clock cycles after the read com- mand, where x = bl/2. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 29: data output timing C t dqsq, t qh, and data valid window (x16) dq (last data valid) 4 dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 ldqs 3 dq (last data valid) 4 dq (first data no longer valid) 4 dq (first data no longer valid) 4 dq[7:0] and ldqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 5 t qh 5 t dqsq 2 t dqsq 2 t dqsq 2 t dqsq 2 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs 3 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq[15:8] and udqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 5 t qh 5 t qh 5 t qh 5 t dqsq 2 t dqsq 2 t dqsq 2 t dqsq 2 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t qh 5 t qh 5 data valid window data valid window data valid window data valid window data valid window upper byte lower byte data valid window notes: 1. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 2. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 3. dq transitioning after dqs transitions define the t dqsq window. ldqs defines the low- er byte and udqs defines the upper byte. 4. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derived for each dqs transitions and is defined as t qh - t dqsq. 7. dq8, dq9, dq10, dq11, dq12, dq13, dq14, or dq15. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 30: data output timing C t dqsq, t qh, and data valid window (x32) dq (last data valid) 4 dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 dqs0/dqs1/dqs2/dqs3 dq (last data valid) dq (first data no longer valid) dq (first data no longer valid) 4 dq and dqs, collectively 6,7 ck ck# byte 0 byte 1 byte 2 byte 3 data valid window data valid window data valid window data valid window t1 t2 t2n t3 t3n t4 t hp 1 t dqsq 2,3 t dqsq 2,3 t dqsq 2,3 t dqsq 2,3 t2 t2n t3 t3n t2 t2n t3 t3n t2 t2n t3 t3n t qh 5 t qh 5 t qh 5 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t qh 5 notes: 1. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 2. dq transitioning after dqs transitions define the t dqsq window. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time; it begins with dqs transition and ends with the last valid dq transition. 4. byte 0 is dq[7:0], byte 1 is dq[15:8], byte 2 is dq[23:16], byte 3 is dq[31:24]. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derived for each dqs transition and is t qh - t dqsq. 7. dq[7:0] and dqs0 for byte 0; dq[15:8] and dqs1 for byte 1; dq[23:16] and dqs2 for byte 2; dq[31:23] and dqs3 for byte 3. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 31: data output timing C t ac and t dqsck ck ck# dqs or ldqs/udqs 2 t0 t1 t2 t3 t4 t5 t2n t3n t4n t5n t6 t rpst t rpre t hz t hz command nop 1 nop 1 nop 1 nop 1 nop 1 all dq values, collectively 3 t3 t2n t4n t5n t5 t ac 4 t ac 4 cl = 3 nop 1 read t2 t lz t lz dont care t3n t4 t dqsck t dqsck notes: 1. commands other than nop can be valid during this cycle. 2. dq transitioning after dqs transitions define t dqsq window. 3. all dq must transition by t dqsq after dqs transitions, regardless of t ac. 4. t ac is the dq output window relative to ck and is the long-term component of dq skew. 512mb: x16, x32 mobile lpddr sdram read operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
write operation write bursts are initiated with a write command, as shown in figure 11 (page 39). the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is ena- bled, the row being accessed is precharged at the completion of the burst. for the write commands used in the following illustrations, auto precharge is disabled. basic data input timing is shown in figure 32 (page 72) (this timing applies to all write op- erations). input data appearing on the data bus is written to the memory array subject to the state of data mask (dm) inputs coincident with the data. if dm is registered low, the corre- sponding data will be written; if dm is registered high, the corresponding data will be ignored, and the write will not be executed to that byte/column location. dm operation is illustrated in figure 33 (page 73). during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be reg- istered on successive edges of dqs. the low state of dqs between the write com- mand and the first rising edge is known as the write preamble; the low state of dqs following the last data-in element is known as the write postamble. the write burst is complete when the write postamble and t wr or t wtr are satisfied. the time between the write command and the first corresponding rising edge of dqs ( t dqss) is specified with a relatively wide range (75%C125% of one clock cycle). all write diagrams show the nominal case. where the two extreme cases (that is, t dqss [min] and t dqss [max]) might not be obvious, they have also been included. figure 34 (page 74) shows the nominal case and the extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored. data for any write burst can be concatenated with or truncated by a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). figure 35 (page 75) shows concatenated bursts of 4. an example of nonconsecutive writes is shown in figure 36 (page 75). full-speed random write accesses within a page or pages can be performed, as shown in figure 37 (page 76). data for any write burst can be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr should be met, as shown in figure 38 (page 77). data for any write burst can be truncated by a subsequent read command, as shown in figure 39 (page 78). note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 40 (page 79). data for any write burst can be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met, as shown in figure 41 (page 80). 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
data for any write burst can be truncated by a subsequent precharge command, as shown in figure 42 (page 81) and figure 43 (page 82). note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 42 (page 81) and figure 43 (page 82). after the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. figure 32: data input timing t dqss t dqsh t wpst t dh t ds t dqsl t dss 3 t dsh 2 t dsh 2 t dss 3 ck ck# t0 1 t1 t1n t2 t2n t3 d in b dont care transitioning data t wpre t wpres dqs 4 dq dm 5 notes: 1. write command issued at t0. 2. t dsh (min) generally occurs during t dqss (min). 3. t dss (min) generally occurs during t dqss (max). 4. for x16, ldqs controls the lower byte; udqs controls the upper byte. for x32, dqs0 controls dq[7:0], dqs1 controls dq[15:8], dqs2 controls dq[23:16], and dqs3 controls dq[31:24]. 5. for x16, ldm controls the lower byte; udm controls the upper byte. for x32, dm0 con- trols dq[7:0], dm1 controls dq[15:8], dm2 controls dq[23:16], and dm3 controls dq[31:24]. 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 33: write C dm operation ck ck# cke a10 ba0, ba1 t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih row t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n nop 1 command active row col n write 2 nop 1 one bank all banks bank x bank x nop 1 nop 1 nop 1 1 pre 3 t dqsl t dqsh t wpst bank x 5 dq 6 dqs dm t ds t dh dont care transitioning data address t wpres t wpre d in n+2 d in n nop 1 note 4 t dqss (nom) t ck notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 in the case shown. 3. pre = precharge. 4. disable auto precharge. 5. bank x at t8 is dont care if a10 is high at t8. 6. d in n = data-in from column n . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 34: write burst dqs t dqss (max) t dqss (nom) t dqss (min) t dqss dm dq 3 ck ck# command write 1,2 nop nop address bank a, col b nop t0 t1 t2 t3 t2n dqs dm dq 3 dqs dm dq 3 d in b dont care transitioning data d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 t dqss t dqss notes: 1. an uninterrupted burst of 4 is shown. 2. a10 is low with the write command (auto precharge is disabled). 3. d in b = data-in for column b . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 35: consecutive write-to-write ck ck# command write 1, 2 nop write 1, 2 nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t1n dq 3 dqs dm dont care transitioning data t dqss (nom) d in b+1 d in b+2 d in b+3 d in n d in n+1 d in n+2 d in n+3 d in b notes: 1. each write command can be to any bank. 2. an uninterrupted burst of 4 is shown. 3. d in b ( n ) = data-in for column b ( n ). figure 36: nonconsecutive write-to-write ck ck# command write 1, 2 nop nop nop nop address bank, col b bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t1n t5n dq 3 dqs dm t dqss (nom) dont care transitioning data d in b+1 d in b+2 d in b+3 d in b d in n+1 d in n+2 d in n+3 write 1,2 d in n notes: 1. each write command can be to any bank. 2. an uninterrupted burst of 4 is shown. 3. d in b ( n ) = data-in for column b ( n ). 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 37: random write cycles t dqss (nom) ck ck# command write 1,2 nop address bank, col b bank, col x bank, col n bank, col g bank, col a t0 t1 t2 t3 t2n t4 t5 t4n t1n t3n t5n dq 3,4 dqs dm dont care transitioning data d in b d in x d in x d in b d in n d in a d in a d in g d in g d in n write 1,2 write 1,2 write 1,2 write 1,2 notes: 1. each write command can be to any bank. 2. programmed bl = 2, 4, 8, or 16 in cases shown. 3. d in b ( or x , n , a , g ) = data-in for column b (or x, n, a, g ). 4. b' (or x, n, a, g ) = the next data-in following d in b ( x, n, a, g ) according to the program- med burst order. 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 38: write-to-read C uninterrupting t dqssnom ck ck# command 1 write 2,3 nop nop read nop nop address bank a, col b bank a, col n nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t6n t wtr 4 cl = 2 dq 5 dqs dm t dqss t dqssmin cl = 2 dq 5 dqs dm t dqss t dqssmax cl = 2 dq 5 dqs dm t dqss dont care transitioning data t5n d in b +1 d in b +2 d in b +3 d in b d in b +1 d in b +2 d in b +3 d in b d in b +1 d in b +2 d in b +3 d in b d out n d out n + 1 d out n d out n + 1 d out n d out n + 1 notes: 1. the read and write commands are to the same device. however, the read and write commands may be to different devices, in which case t wtr is not required and the read command could be applied earlier. 2. a10 is low with the write command (auto precharge is disabled). 3. an uninterrupted burst of 4 is shown. 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. d in b = data-in for column b ; d out n = data-out for column n . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 39: write-to-read C interrupting t dqss (nom) ck ck# command write 1,2 nop nop nop nop nop address bank a, col b bank a, col n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t6 t6n cl = 3 dq 5 dqs 4 dm t dqss (min) cl = 3 dq 5 dqs 4 dm t dqss (max) cl = 3 dq 5 dqs 4 dm dont care transitioning data t dqss t dqss t dqss d in b+1 d in b d in b+1 d in b d in b+1 d in b d out n d out n + 1 d out n d out n + 1 d out n d out n + 1 t wtr 3 notes: 1. an interrupted burst of 4 is shown; 2 data elements are written. 2. a10 is low with the write command (auto precharge is disabled). 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. dqs is required at t2 and t2n (nominal case) to register dm. 5. d in b = data-in for column b ; d out n = data-out for column n . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 40: write-to-read C odd number of data, interrupting t dqss (nom) ck ck# command 1 write 2 nop nop nop nop nop address bank a, col b bank a, col b read t0 t1 t2 t3 t2n t4 t5 t5n t1n t6 t6n t wtr 3 cl = 3 dq 5 dqs 4 dm t dqss (min) cl = 3 dq 5 dqs 4 dm t dqss (max) cl = 3 dq 5 dqs 4 dm dont care transitioning data t dqss t dqss t dqss d in b d out n d out n + 1 d in b d in b d out n d out n + 1 d out n d out n + 1 notes: 1. an interrupted burst of 4 is shown; 1 data element is written, 3 are masked. 2. a10 is low with the write command (auto precharge is disabled). 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. dqs is required at t2 and t2n (nominal case) to register dm. 5. d in b = data-in for column b ; d out n = data-out for column n . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 41: write-to-precharge C uninterrupting ck ck# command 1 write 2,4 nop nop nop nop address bank a, col b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 dq 6 dqs dm dq 6 dqs dm dq 6 dqs dm dont care transitioning data t wr 5 pre 3,4 t dqss (nom) t dqss (min) t dqss (max) t dqss t dqss t dqss d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 notes: 1. an uninterrupted burst 4 of is shown. 2. a10 is low with the write command (auto precharge is disabled). 3. pre = precharge. 4. the precharge and write commands are to the same device. however, the pre- charge and write commands can be to different devices; in this case, t wr is not re- quired and the precharge command can be applied earlier. 5. t wr is referenced from the first positive ck edge after the last data-in pair. 6. d in b = data-in for column b . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 42: write-to-precharge C interrupting t dqss (nom) ck ck# command 1 write 2 nop nop nop nop address bank a, col b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 dq 6 dqs 5 dm t dqss t dqss (min) dq 6 dqs 5 dm t dqss t dqss (max) dq 6 dqs 5 dm t dqss dont care transitioning data t wr 4 pre 3 t4n t3n d in b d in b + 1 d in b d in b + 1 d in b d in b + 1 notes: 1. an interrupted burst of 8 is shown; two data elements are written. 2. a10 is low with the write command (auto precharge is disabled). 3. pre = precharge. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. dqs is required at t4 and t4n to register dm. 6. d in b = data-in for column b . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 43: write-to-precharge C odd number of data, interrupting t dqss (nom) ck ck# command 1 write 2 nop nop nop nop address bank a, col b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 dq 7 dqs 5, 6 dm 6 t dqss (min) dq 7 dqs 5, 6 dm 6 t dqss (max) dq 7 dqs 5, 6 dm 6 t dqss t dqss t dqss dont care transitioning data d in b d in b d in b t wr 4 pre 3 t4n t3n notes: 1. an interrupted burst of 8 is shown; one data element is written. 2. a10 is low with the write command (auto precharge is disabled). 3. pre = precharge. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. dqs is required at t4 and t4n to register dm. 6. if a burst of 4 is used, dqs and dm are not required at t3, t3n, t4, and t4n. 7. d in b = data-in for column b . 512mb: x16, x32 mobile lpddr sdram write operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
precharge operation the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 deter- mines whether one or all banks will be precharged, and in the case where only one bank is precharged (a10 = low), inputs ba0 and ba1 select the bank. when all banks are pre- charged (a10 = high), inputs ba0 and ba1 are treated as dont care. after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature that performs the same individual bank precharge func- tion described previously, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent; it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. this earliest valid stage is determined as if an explicit precharge command was issued at the earliest possible time without violating t ras (min), as described for each burst type in table 19 (page 44). the read with auto precharge enabled state or the write with auto precharge enabled state can each be broken into two parts: the ac- cess period and the precharge period. the access period starts with registration of the command and ends where t rp (the precharge period) begins. for read with auto pre- charge, the precharge period is defined as if the same burst was executed with auto pre- charge disabled, followed by the earliest possible precharge command that still ac- cesses all the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. in addi- tion, during a write with auto precharge, at least one clock is required during t wr time. during the precharge period, the user must not issue another command to the same bank until t rp is satisfied. this device supports t ras lock-out. in the case of a single read with auto precharge or single write with auto precharge issued at t rcd (min), the internal precharge will be delayed until t ras (min) has been satisfied. bank read operations with and without auto precharge are shown in figure 44 (page 85) and figure 45 (page 86). bank write operations with and without auto precharge are shown in figure 46 (page 87) and figure 47 (page 88). 512mb: x16, x32 mobile lpddr sdram precharge operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
concurrent auto precharge this device supports concurrent auto precharge such that when a read with auto pre- charge is enabled or a write with auto precharge is enabled, any command to another bank is supported, as long as that command does not interrupt the read or write data transfer already in process. this feature enables the precharge to complete in the bank in which the read or write with auto precharge was executed, without requiring an explicit precharge command, thus freeing the command bus for operations in other banks. 512mb: x16, x32 mobile lpddr sdram auto precharge pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 44: bank read C with auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih row t rcd t ras t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 4,5 dqs 4 case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 4,5 dqs 4 t hz (max) nop 1 nop 1 command active row col n read 2 bank x row row bank x active bank x nop 1 nop 1 nop 1 dont care transitioning data address nop 1 t rpre t dqsck (max) t ac (max) d out n d out n + 1 d out x d out x + 1 d out n d out n + 1 d out x d out x + 1 t dqsck (min) t ac (min) t lz (min) t rpre t rpst t lz (min) note 3 t rpst notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 in the case shown. 3. enable auto precharge. 4. refer to figure 29 (page 68) and figure 30 (page 69) for detailed dqs and dq timing. 5. d out n = data-out from column n . 512mb: x16, x32 mobile lpddr sdram auto precharge pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 45: bank read C without auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t ih t is t ih t is t ih t is t ih t is t ih row t rcd t ras 6 t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 7,8 dqs 7 case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 7,8 dqs 7 t hz (max) nop 1 nop 1 command active row col n read 2 bank x row row bank x active bank x nop 1 nop 1 nop 1 dont care transitioning data address pre 3 bank x 5 t rpre t rpre t ac (max) all banks one bank d out n d out n + 1 d out n + 2 d out n + 3 d out n d out n + 1 d out n + 2 d out n + 3 t lz (min) t lz (min) t dqsck (min) t ac (min) t rpst t rpst t dqsck (max) note 4 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 in the case shown. 3. pre = precharge. 4. disable auto precharge. 5. bank x at t5 is dont care if a10 is high at t5. 6. the precharge command can only be applied at t5 if t ras (min) is met. 7. refer to figure 29 (page 68) and figure 30 (page 69) for dqs and dq timing details. 8. d out n = data out from column n. 512mb: x16, x32 mobile lpddr sdram auto precharge pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 46: bank write C with auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih row t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n nop 4 nop 4 command note 3 active row col n write 2 nop 4 bank x nop 4 bank x nop 4 nop 4 nop 4 t dqsl t dqsh t wpst dq 1 dqs dm d in b t ds t dh t dqss (nom) dont care transitioning data t wpres t wpre address notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 in the case shown. 3. enable auto precharge. 4. d in n = data-out from column n . 512mb: x16, x32 mobile lpddr sdram auto precharge pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 47: bank write C without auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih row t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n no p 1 no p 1 command active row col n write 2 nop 1 one bank all banks bank x pre 3 bank x nop 1 nop 1 nop 1 t dqsl t dqsh t wpst bank x 5 dq 6 dqs dm d in b t ds t dh dont care transitioning data t dqss (nom) t wpre t wpres address note 4 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 in the case shown. 3. pre = precharge. 4. disable auto precharge. 5. bank x at t8 is dont care if a10 is high at t8. 6. d out n = data-out from column n . 512mb: x16, x32 mobile lpddr sdram auto precharge pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
auto refresh operation auto refresh mode is used during normal operation of the device and is analogous to cas#-before-ras# (cbr) refresh in fpm/edo dram. the auto refresh com- mand is nonpersistent and must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a dont care during an auto refresh command. for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. the auto refresh period begins when the auto refresh command is registered and ends t rfc later. figure 48: auto refresh mode ck cke ck# command 1 nop 2 valid valid nop 2 nop 2 pre row a10 ba0, ba1 bank(s) 5 bank ar nop 2, 3 ar 4 nop 2, 3 active nop 2 one bank all banks t ck t ch t cl t is t is t ih t ih row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq 6 dm 6 dqs 6 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rfc 4 t rp t rfc t0 t1 t2 t3 t4 t a 0 tb0 t a 1 tb1 tb2 dont care ) ) ( ) ( ) address ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ( ) ) notes: 1. pre = precharge; ar = auto refresh. 2. nop commands are shown for ease of illustration; other commands may be valid during this time. cke must be active during clock positive transitions. 3. nop or command inhibit are the only commands supported until after t rfc time; cke must be active during clock positive transitions. 4. the second auto refresh is not required and is only shown as an example of two back-to-back auto refresh commands. 5. bank x at t1 is dont care if a10 is high at this point; a10 must be high if more than one bank is active (for example, must precharge all active banks). 6. dm, dq, and dqs signals are all dont care/high-z for operations shown. although it is not a jedec requirement, cke must be active (high) during the auto re- fresh period to provide support for future functional features. the auto refresh period begins when the auto refresh command is registered and ends t rfc later. 512mb: x16, x32 mobile lpddr sdram auto refresh operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
self refresh operation the self refresh command can be used to retain data in the device while the rest of the system is powered down. when in self refresh mode, the device retains data without external clocking. the self refresh command is initiated like an auto refresh command, except that cke is disabled (low). all command and address input signals except cke are dont care during self refresh. during self refresh, the device is refreshed as defined in the extended mode register. (see partial-array self refresh (page 56).) an internal temperature sensor adjusts the re- fresh rate to optimize device power consumption while ensuring data integrity. (see temperature-compensated self refresh (page 55).) the procedure for exiting self refresh requires a sequence of commands. first, ck must be stable prior to cke going high. when cke is high, the device must have nop commands issued for t xsr to complete any internal refresh already in progress. during self refresh operation, refresh intervals are scheduled internally and may vary. these refresh intervals may differ from the specified t refi time. for this reason, the self refresh command must not be used as a substitute for the auto refresh command. 512mb: x16, x32 mobile lpddr sdram self refresh operation pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 49: self refresh mode ck 1 ck# command nop ar 3 address cke 1,2 valid dq dm dqs valid nop t rp 4 t ch t cl t ck t is t xsr 5 t is t ih t ih t is t is t ih t is enter self refresh mode exit self refresh mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 tb0 ta1 ( ) ( ) ( ) ( ) dont care ( ) ( ) ( ) ( ) t a0 1 ( ) ( ) t cke notes: 1. clock must be stable, cycling within specifications by ta0, before exiting self refresh mode. 2. cke must remain low to remain in self refresh. 3. ar = auto refresh. 4. device must be in the all banks idle state prior to entering self refresh mode. 5. either a nop or deselect command is required for t xsr time with at least two clock pulses. power-down power-down is entered when cke is registered low. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates all input and output buffers, including ck and ck# and excluding cke. exiting power-down requires the device to be at the same voltage as when it entered power-down and received a stable clock. note that the power-down du- ration is limited by the refresh requirements of the device. when in power-down, cke low must be maintained at the inputs of the device, while all other input signals are dont care. the power-down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command). nop or deselect commands must be maintained on the command bus until t xp is satisfied. see figure 51 (page 93) for a detailed illustration of power-down mode. 512mb: x16, x32 mobile lpddr sdram power-down pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 50: power-down entry (in active or precharge mode) cs# ras#, cas#, we# cke ck ck# dont care address ras#, cas#, we# cs# ba0, ba1 or 512mb: x16, x32 mobile lpddr sdram power-down pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 51: power-down mode (active or precharge) ck ck# command v alid 2 nop address cke dq dm dqs t ck t ch t cl t is t is t ih t is t is t ih t ih enter 3 powe r -down mode exit power-down mode must not exceed refresh device limits ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 ta0 ta1 ta2 t2 nop dont care ( ) ( ) ( ) ( ) valid tb1 t xp 1 t cke 1 t cke valid no read/write access in progress valid ( ) ( ) notes: 1. t cke applies if cke goes low at ta2 (entering power-down); t xp applies if cke remains high at ta2 (exit power-down). 2. if this command is a precharge (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. if this command is an active (or if at least 1 row is already active), then the power-down mode shown is active power- down. 3. no column accesses can be in progress when power-down is entered. deep power-down deep power-down (dpd) is an operating mode used to achieve maximum power reduc- tion by eliminating power to the memory array. data will not be retained after the de- vice enters dpd mode. before entering dpd mode the device must be in the all banks idle state with no activity on the data bus ( t rp time must be met). dpd mode is entered by holding cs# and we# low with ras# and cas# high at the rising edge of the clock while cke is low. cke must be held low to maintain dpd mode. the clock must be stable prior to exiting dpd mode. to exit dpd mode, assert cke high with either a nop or deselect com- mand present on the command bus. after exiting dpd mode, a full dram initialization sequence is required. 512mb: x16, x32 mobile lpddr sdram power-down pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 52: deep power-down mode t is all banks idle with no activity on the data bus exit deep power-down mode enter deep power-down mode cke ck ck# command 1 dpd 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop nop pre 3 t0 t1 t2 t a0 1 ta1 ta2 nop dont care t cke ta3 t = 200s notes: 1. clock must be stable prior to cke going high. 2. dpd = deep power-down. 3. upon exit of deep power-down mode, a full dram initialization sequence is required. 512mb: x16, x32 mobile lpddr sdram power-down pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
clock change frequency one method of controlling the power efficiency in applications is to throttle the clock that controls the device. the clock can be controlled by changing the clock frequency or stopping the clock. the device enables the clock to change frequency during operation only if all timing pa- rameters are met and all refresh requirements are satisfied. the clock can be stopped altogether if there are no dram operations in progress that would be affected by this change. any dram operation already in process must be completed before entering clock stop mode; this includes the following timings: t rcd, t rp, t rfc, t mrd, t wr, and t rpst. in addition, any read or write burst in progress must be complete. (see read operation and write operation.) cke must be held high with ck = low and ck# = high for the full duration of the clock stop mode. one clock cycle and at least one nop or deselect is required after the clock is restarted before a valid command can be issued. figure 53: clock stop mode exit clock stop mode cke ck ck# command ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop nop t a 1 t a 2 tb3 tb4 dont care address dq, dqs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) enter clock stop mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) cmd 2 v ali d cmd 2 v ali d nop 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all dram activities must be complete ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) notes: 1. prior to ta1, the device is in clock stop mode. to exit, at least one nop is required before issuing any valid command. 2. any valid command is supported; device is not in clock suspend mode. 512mb: x16, x32 mobile lpddr sdram clock change frequency pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
revision history rev. h C 06/13 ? added note to reduced page size option: contact factory for availability rev. g C 10/11 ? added note to t rc parameter in electrical specs C ac operating conditions table rev. f C 10/11 ? deleted low power option and marking on front page ? deleted low power option and marking in part numbering table ? deleted low power column in i dd6 specifications and conditions table rev. e C 6/11 ? updated 60- and 90-ball package drawings rev. d C 4/11 ? updated low-power i dd values for i dd6 rev. c C 1/11 ? added automotive temperature information rev. b C 02/10 ? changed i dd6 table rev. a C 01/10 ? initial release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 512mb: x16, x32 mobile lpddr sdram revision history pdf: 09005aef83dd2b3e t67m_512mb_mobile_lpddr.pdf - rev. h 06/13 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.


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